Phase locked loop for high speed data capture of a serial data stream

• US 5,633,899 A
• Filed: 02/02/1996
• Issued: 05/27/1997
• Est. Priority Date: 02/02/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Mactaggart, Iain R., Fiedler, Alan, Welch, James R.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US08/596,006
• Time in Patent Office: 480 Days
• Field of Search: 375/376, 375/374, 331/1 A, 327/149, 327/150, 327/158, 327/159
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Claims

1. A phase locked loop for locking on to a phase and frequency of a serial data stream, comprising:

a data input for receiving the serial data stream;

a multiple-bit latch having a plurality of designated data and boundary-detect latch elements, with each latch element comprising a latch input coupled to the data input, a sample clock input, and a latch output;

a multiple-stage voltage controlled oscillator having a voltage control input, a plurality of sample clock outputs, and an adjustable delay between each sample clock output, wherein each sample clock output is coupled to a corresponding sample clock input;

a phase detection circuit having phase detect inputs coupled to the latch outputs and having a phase control output; and

a feedback circuit coupled between the phase control output and the voltage control input.

2. The phase locked loop of claim 1 and further comprising:

a data recovery storage element having a plurality of data recovery inputs which are coupled to respective latch outputs of the designated data latch elements and having a recovery clock input which is coupled to one of the plurality of sample clock outputs.

3. The phase locked loop of claim 1 wherein each latch element comprises a level sensitive differential capture latch.

4. The phase locked loop of claim 1 wherein each latch element comprises an edge triggered flip-flop.

5. The phase locked loop of claim 1 wherein the serial data stream has a data transition frequency and the adjustable delay between each sample clock output is an inverse of an even number multiple of the data transition frequency.

6. The phase locked loop of claim 5 wherein the serial data stream has a data transition frequency and the adjustable delay is an inverse of twice the data transition frequency.

7. The phase locked loop of claim 1 wherein the serial data stream is divided into groups of N bits of data and wherein the multiple-bit latch comprises an even number of latch elements per bit of data.

8. The phase locked loop of claim 7 wherein the multiple-bit latch comprises N designated data latch elements and N designated boundary-detect latch elements.

9. The phase locked loop of claim 1 wherein:

the voltage controlled oscillator generates a sample clock signal on the sample clock outputs which has a plurality of clock cycles, with each clock cycle having a positive phase and a negative phase; and

the designated data and boundary-detect latch elements comprise first and second groups, with the designated data and boundary-detect latch elements in the first group preceding the designated data and boundary-detect latch elements in the second group in time, wherein the sample clock inputs of the first group are active on the positive phase and sample clock inputs of the second group are active on the negative phase.

10. The phase locked loop of claim 1 wherein:

each designated boundary-detect latch element is bounded in time by a designated previous in time data latch element and a designated subsequent in time data latch element; and

the phase detection circuit comprises;

up phase control means coupled between the latch outputs of the designated previous in time data latch element and the designated boundary-detect latch element for generating an up phase control signal on the phase control output when the latch outputs of the designated previous in time data latch element and the designated boundary-detect latch element have different logic states; and

down phase control means coupled between the latch outputs of the designated boundary-detect latch element and the designated subsequent in time data latch element for generating a down phase control signal on the phase control output when the latch outputs of the designated boundary-detect latch element and the designated subsequent in time data latch element have different logic states.

11. The phase locked loop of claim 10 wherein the feedback circuit comprises means for generating a voltage on the voltage control input as a function of the up and down phase control signals.

12. The phase locked loop of claim 1 wherein the feedback circuit comprises:

a charge pump having a charge pump input coupled to the phase control output and having a charge pump output; and

a loop filter coupled between the charge pump output and the voltage control input.

13. The phase locked loop of claim 1 wherein:

each designated boundary-detect latch element is bounded in time by a designated previous in time data latch element and a designated subsequent in time data latch element; and

the phase detection circuit comprises;

an up exclusive-OR logic gate coupled between each designated previous in time data latch element and each designated boundary-detect latch element and having an up phase control output; and

a down exclusive-OR logic gate coupled between each designated subsequent in time data latch element and each designated boundary-detect latch element and having a down phase control output.

14. The phase locked loop of claim 13 wherein the phase detection circuit further comprises voting means for comparing a number of the up phase control outputs having a logic true state and a number of the down phase control outputs having a logic true state and for generating a comparison output on the phase control output of the phase detection circuit as a function of the comparison.

15. A system for data capture and clock recovery of a serial data stream, comprising:

a data input for receiving the serial data stream;

a multiple-bit latch having a plurality of designated data and boundary-detect latch elements, with each latch element comprising a latch input coupled to the data input, a sample clock input, and a latch output;

a multiple-stage voltage controlled oscillator having a voltage control input, a plurality of sample clock outputs, and an adjustable delay between each sample clock output, wherein each sample clock output is coupled to a corresponding sample clock input;

a phase detection circuit having phase detect inputs coupled to the latch outputs and having a phase control output;

a phase locked feedback loop coupled between the phase control output and the voltage control input; and

a data recovery storage element having a plurality of data recovery inputs which are coupled to respective latch outputs of the designated data latch elements and having a recovery clock input which is coupled to one of the plurality of sample clock outputs.

16. A method of locking onto a phase and frequency of a serial input signal, comprising:

applying the serial input signal to a multiple-bit latch comprising a boundary detect latch element, a previous in time data latch element and a subsequent in time data latch element, wherein each latch element comprises a latch output;

generating a first sample clock, a second sample clock which is delayed from the first sample clock by a delay, and a third sample clock which is delayed from the second sample clock by the delay;

operating the previous data latch element with the first sample clock, the boundary-detect latch element with the second sample clock and the subsequent data latch element with the third sample clock;

decreasing the delay if the latch outputs of the previous in time data latch element and the boundary-detect latch element have different logic states; and

increasing the delay if the latch outputs of the boundary-detect latch element and the subsequent in time data latch element have different logic states.

17. The method of claim 16 and further comprising:

clocking the latch outputs of the previous and subsequent in time data latch elements into a data recovery storage element as a function of at least one of the first, second and third sample clocks.

18. The method of claim 16 wherein the serial input stream has a transition frequency and the step of generating the first, second and third sample clocks comprises maintaining the delay at an inverse of an even number multiple of the transition frequency.

19. The method of claim 18 wherein the step of generating the first, second and third sample clocks comprises maintaining the delay at an inverse of twice the data transition frequency.