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Microprocessor point-to-point communication

  • US 5,634,043 A
  • Filed: 08/25/1994
  • Issued: 05/27/1997
  • Est. Priority Date: 08/25/1994
  • Status: Expired due to Term
First Claim
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1. A phase-tolerant communication scheme, comprising:

  • a first computing resource generating a first clock signal;

    a first clock line coupled to the first computing resource for communicating the first clock signal from the first computing resource;

    a first plurality of data lines coupled to the first computing resource for communicating data from the first computing resource; and

    a second computing resource coupled to the first plurality of data lines and to the first clock line, the second computing resource generating a second clock signal with an unknown phase relationship to the first clock signal, the second computing resource comprising;

    a first buffer coupled to the first plurality of data lines,a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal,a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, anda first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal;

    wherein data from the first computing resource is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer.

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