Microprocessor point-to-point communication
First Claim
1. A phase-tolerant communication scheme, comprising:
- a first computing resource generating a first clock signal;
a first clock line coupled to the first computing resource for communicating the first clock signal from the first computing resource;
a first plurality of data lines coupled to the first computing resource for communicating data from the first computing resource; and
a second computing resource coupled to the first plurality of data lines and to the first clock line, the second computing resource generating a second clock signal with an unknown phase relationship to the first clock signal, the second computing resource comprising;
a first buffer coupled to the first plurality of data lines,a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal,a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, anda first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal;
wherein data from the first computing resource is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer.
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Accused Products
Abstract
A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into "clusters" wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.
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Citations
32 Claims
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1. A phase-tolerant communication scheme, comprising:
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a first computing resource generating a first clock signal; a first clock line coupled to the first computing resource for communicating the first clock signal from the first computing resource; a first plurality of data lines coupled to the first computing resource for communicating data from the first computing resource; and a second computing resource coupled to the first plurality of data lines and to the first clock line, the second computing resource generating a second clock signal with an unknown phase relationship to the first clock signal, the second computing resource comprising; a first buffer coupled to the first plurality of data lines, a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal, a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, and a first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal; wherein data from the first computing resource is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer system, comprising:
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a processor generating a first clock signal; a first clock line coupled to the processor for communicating the first clock signal; a first plurality of data lines coupled to the processor for communicating data from the processor; and a memory coupled to the first plurality of data lines and to the first clock line, the memory generating a second clock signal with an unknown phase relationship to the first clock signal, the memory comprising; a first buffer coupled to the first plurality of data lines, a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal, a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, and a first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal; wherein data from the processor is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A multi-processor system, comprising:
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a first processor generating a first clock signal; a first clock line coupled to the first processor for communicating the first clock signal; a first plurality of data lines coupled to the first processor for communicating data from the first processor; and a second processor coupled to the first plurality of data lines and to the first clock line, the second processor generating a second clock signal with an unknown phase relationship to the first clock signal, the second processor comprising; a first buffer coupled to the first plurality of data lines, a first control circuit coupled to the first clock line that generates a first delayed clock signal in response to the first clock signal, a first write pointer circuit coupled to the first clock line that generates a first write pointer in response to the first clock signal, and a first read pointer circuit coupled to the first control circuit that generates a first read pointer in response to the first delayed clock signal; wherein data from the first processor is stored in the first buffer according to the first write pointer and data is read from the first buffer according to the first read pointer. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification