System and method for behavioral description translation

• US 5,634,115 A
• Filed: 12/13/1994
• Issued: 05/27/1997
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fitzpatrick, Daniel, Kundert, Kenneth S.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Roberts, Andrew S.
• Application Number:
  US08/355,058
• Time in Patent Office: 896 Days
• Field of Search: 364/488, 364/489, 364/578, 395/500
• US Class Current: 716/103
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A behavioral description translation method is disclosed wherein output and input access functions are identified from behavioral descriptions of the underlying circuit and its components. Structural representations of the behavioral descriptions of the circuits components as identified by the access functions are constructed therefrom from a set of branch primitives provided. From the constructed branches, those S-type branches, i.e., voltage sources and current probes, that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches are collapsed. Those P-type branches, i.e., the current sources and voltage probes, that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches are collapsed. Then, for every node in the circuit a single relationship that expresses KCL is generated from the collapsed branch relationships. The relationships thus formed are combined to eliminate un-necessary branch relationships to be provided to the circuit simulator. In such a manner, the higher-level behavioral descriptions can be effectively translated into a lower-level specification which describes the circuit to a simulator program.

Claims

1. A method of behavioral description translation of higher-level behavioral descriptions into lower-level specifications to describe a circuit and its components to a simulator system such that users treat voltages and currents symmetrically when formulating the higher-level behavioral descriptions, the method comprising the steps of:

receiving a higher level behavioral description describing voltages and currents symmetrically and identifying access functions contained therein;

constructing at least one structural representation for a component in a circuit from said access functions according to a set of pre-defined primitives such that said at least one structural representation contains a branch internal to said each component that describes behavior of said each component;

generating branch relationships from said constructed structural representations;

eliminating unnecessary branch relationships to produce a reduced relationship set; and

providing said reduced relationship set to a simulator system.

2. A method for behavioral description translation of higher-level behavioral descriptions of a circuit to a lower-level specification for a circuit simulator system such that users treat voltages and currents symmetrically when formulating the higher-level behavioral description, the method comprising the steps of:

identifying all access functions in a higher-level behavioral description wherein said higher-level behavioral description describes voltages and currents symmetrically;

constructing a structural representation for each component in a circuit from identified access functions such that said structural representation contains a branch internal to said each component that describes behavior of said each component;

from the structural representations, performing the steps of;

collapsing all S-type branches connected in series between a pair of nodes into one new branch where voltage on the new branch is a sum of voltages of said all S-type branches; and

collapsing all P-type branches connected in parallel between another pair of nodes into one second new branch where current through the second new branch is a sum of currents of said all P-type branches;

from said first new and second new branches, generating a set of branch relationships describing said circuit;

combining the generated set of branch relationships to eliminate unnecessary branch relationships therefrom; and

providing said reduced relationship set to said circuit simulator system.

3. A method as defined in claim 2 wherein said access functions are selected from a set of voltage and current functions identified in a contribution statement in said higher-level behavioral description.

4. A method as defined in claim 3 where output access functions are used to specify signals and are found on the left-hand side of the contribution statement and input access functions are used to monitor signals and are found in expressions on the right hand side of the contribution statement such that output access functions are controlled sources and input access functions are probes.

5. A method as defined in claim 4 wherein signals produced by said sources are controlled by signals measured by said probes in a manner specified by the contribution statement.

6. A method as defined in claim 2 wherein said structural representations are constructed using one or more primitive branch types from a set containing voltage probes, current probes, voltage sources, and current sources.

7. A method as defined in claim 2 wherein said structural representations comprise a list of all of components in said circuit coupled with parametric information and terminal information.

8. A method as defined in claim 2 wherein a combination of said structural representations comprise a netlist.

9. A method as defined in claim 6 wherein said sources and said probes are S-type branches (voltage sources and current probes) and combine in series when from the same component and attached to the same two nodes.

10. A method as defined in claim 6 wherein said sources and said probes are P-type branches (current sources and voltage probes) and combine in parallel when from the same component and attached to the same two nodes.

11. A method as defined in claim 2 wherein said generated set of relationships further comprises a combination of three sets of relationships:

nodal analysis relationships of KCL;

constitutive relationships for P-type branches; and

constitutive relationships for S-type branches.

15. A method as defined in claim 5 wherein said higher level behavioral description permits Ohm'"'"'s Law to be expressed in said contribution statement with an input current probe and equivalently in a second contribution statement with an input voltage probe.

16. A method as defined in claim 15 wherein said each component is chosen from a group consisting of a resistor, a capacitor, an inductors, a conductance, and a transistor.

17. A method as defined in claim 16 wherein said circuit includes an RLC circuit.

18. A method as defined in claim 5 wherein said higher level behavioral description permits Faraday'"'"'s Law of Inductance to be expressed in said contribution statement with an input current probe and equivalently in a second contribution statement with an input voltage probe.

19. A method as defined in claim 2 wherein on each S-type branch of said all S-type branches, said voltage on said each S-type branch is a function of a voltage in said circuit and a current in said circuit, and wherein at least one of said all S-type branches is a conditional S-type branch such that a sum of voltages on said each S-type branch is a difference between a voltage at a first node of said conditional S-type branch and a voltage at a second node of said conditional S-type branch when an S-type driver is active and is a current through said conditional S-type branch when no S-type drivers are active.

20. A method as defined in claim 2 wherein on each P-type branch of said all P-type branches, said voltage on said each P-type branch is a function of a voltage in said circuit and a current in said circuit, and wherein at least one of said all P-type branches is a conditional P-type branch such that a sum of voltages on said each S-type branch is a difference between a voltage at a first node of said conditional S-type branch and a voltage at a second node of said conditional S-type branch when an S-type driver is active and is a current through said conditional S-type branch when no S-type drivers are active.

12. A computer circuit simulation system for behavioral description translation of a higher-level behavioral description into a lower-level specification such that users of the computer circuit simulation system can treat voltages and currents symmetrically when formulating the higher-level behavioral description, the computer circuit simulation system comprising:

a computer processor unit;

memory media storage connected to said computer processor; and

a computer program in communication with said memory media storage and said computer processor unit performing the operation of;

identifying all access functions in the higher-level behavioral description wherein said higher-level behavioral desorption describes voltages and currents symmetrically;

constructing a structural representation for each component in a circuit from identified access functions such that said structural representation contains a branch internal to said each component that describes behavior of said each component from the structural representations, performing the steps of;

collapsing all S-type branches connected in series between a pair of nodes into one new branch where voltage on the new branch is a sum of voltages of said all S-type branches; and

collapsing all P-type branches connected in parallel between another pair of nodes into one second new branch where current through the second new branch is a sum of currents of said all P-type branches;

from said first new and second new branches, generating a set of branch relationships describing said circuit; and

combining the generated set of branch relationships to eliminate unnecessary branch relationships therefrom.

13. A computer circuit simulation system as defined in claim 12 wherein said higher-level behavioral descriptions are supplied by a supplied computer program syntax using a modeling language.

14. A computer circuit simulation system as defined in claim 12 wherein said system is implemented using a SpectreHDL behavioral modeling language.

21. A computer circuit simulation system as defined in claim 12 wherein said access functions are selected from a set of voltage and current functions identified in a contribution statement in said higher-level behavioral description.

22. A computer circuit simulation system as defined in claim 21 where output access functions are used to specify signals and are found on the left-hand side of the contribution statement and input access functions are used to monitor signals and are found in expressions on the right hand side of the contribution statement such that output access functions are controlled sources and input access functions are probes.

23. A computer circuit simulation system as defined in claim 22 wherein signals produced by said sources are controlled by signals measured by said probes in a manner specified by the contribution statement.

24. A computer circuit simulation system as defined in claim 12 wherein said structural representations are constructed using one or more primitive branch types from a set containing voltage probes, current probes, voltages sources, and current sources.

25. A computer circuit simulation system as defined in claim 12 wherein said structural representations comprise a list of all of components in said circuit coupled with parametric information and terminal information.

26. A computer circuit simulation system as defined in claim 12 wherein a combination of structural representations comprise a netlist.

27. A computer circuit simulation system as defined in claim 24 wherein said sources and said probes are S-type branches (voltage sources and current probes) and combine in series when from the same component and attached to the same component and attached to the same two nodes.

28. A computer circuit simulation system as defined in claim 24 wherein said sources and said probes are P-type branches (current sources and voltage probes) and combine in parallel when from the same component and attached to the same component and attached to the same two nodes.