Porous silicon trench and capacitor structures

• US 5,635,419 A
• Filed: 05/04/1995
• Issued: 06/03/1997
• Est. Priority Date: 10/28/1994
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Geiss, Peter J., Kenney, Donald M.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/435,028
• Time in Patent Office: 761 Days
• Field of Search: 437/60, 437/71, 437/919, 437/977, 437/978, 148/DIG. 14, 148/DIG. 138
• US Class Current: 438/386
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: Y10S 438/96 Porous semiconductor
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/899 Electrolytic

Abstract

The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalls thereof. Such a trench can then be utilized to form a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.

Claims

1. A method of forming a semiconductor capacitor structure, said method comprising:

forming a substrate of monocrystalline silicon, said substrate having an upper portion and a lower portion, said upper portion having a low conductivity and said lower portion having a high conductivity;

anodically etching said substrate of silicon so as to form porous silicon within said lower portion of said substrate;

forming a conformal layer of a dielectric material overlying said porous silicon; and

forming a conformal layer of silicon overlying said layer of dielectric material;

wherein said porous silicon forms a first plate of a capacitor structure and said conformal layer of silicon forms a second plate of said capacitor structure, said first plate separated from said second plate by said dielectric material.

2. The method of claim 1 wherein said conformal layer of dielectric material comprises multi-layer dielectric material.

3. The method of claim 1 wherein said lower portion of said substrate comprised of monocrystalline silicon comprises p+ monocrystalline silicon.

4. The method of claim 2 wherein said multi-layer dielectric material is selected from the group consisting of oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

5. The method of claim 1 wherein said conformal layer of silicon comprises polysilicon.

6. The method of claim 1 wherein said forming of a conformal layer of a dielectric material comprises deposition or thermal growth of said conformal layer of dielectric material.

7. The method of claim 6 wherein said deposition comprises chemical vapor deposition.

8. The method of claim 1 wherein said forming of a conformal layer of silicon comprises deposition of said conformal layer of silicon.

9. The method of claim 8 wherein said deposition comprises chemical vapor deposition.

31. The method of claim 1 wherein said upper portion of said semiconductor substrate of monocrystalline silicon comprises n-doped monocrystalline silicon.

32. The method of claim 1 wherein said upper portion of said semiconductor substrate of monocrystalline silicon comprises p- monocrystalline silicon.

33. The method of claim 1 wherein anodically etching said substrate of silicon comprises confining said porous silicon essentially to said lowest portion of said substrate.

10. A method of forming a trench capacitor structure, said method comprising:

forming a trench in a monocrystalline silicon substrate, said substrate comprising an upper portion and a lower portion, said upper portion having a low conductivity and said lower portion having a high conductivity;

anodically etching said silicon substrate surrounding said trench so as to form porous silicon within said lower portion of said substrate;

forming a conformal layer of a dielectric material overlying said porous silicon; and

forming a conformal layer of silicon overlying said layer of dielectric material;

wherein said porous silicon forms a first plate of a capacitor structure and said conformal layer of silicon forms a second plate of said capacitor structure, said first plate separated from said second plate by said layer of dielectric material.

11. The method of claim 10 wherein said lower portion of said monocrystalline silicon substrate comprises p+ monocrystalline silicon.

12. The method of claim 10 wherein said dielectric material comprises a multi-layer dielectric material.

13. The method of claim 10 wherein said dielectric material is selected from the group consisting of nitride, oxide, oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

14. The method of claim 10 wherein said conformal layer of silicon comprises polysilicon.

15. The method of claim 10 wherein said forming of a conformal layer of a dielectric material comprises deposition of said conformal layer of dielectric material.

16. The method of claim 15 wherein said deposition comprises chemical vapor deposition.

17. The method of claim 10 wherein said forming of a conformal layer of silicon comprises deposition of said conformal layer of silicon.

18. The method of claim 17 wherein said deposition comprises chemical vapor deposition.

34. The method of claim 10 wherein anodically etching said silicon substrate comprises confining said porous silicon essentially to said lower portion of said substrate.

19. A self-limiting method of forming isolated adjacent trenches in a substrate, said method comprising:

forming a pair of adjacent trenches in a monocrystalline silicon substrate;

anodically etching said silicon substrate surrounding each of said adjacent trenches so as to form a pair of porous silicon regions;

wherein said anodic etching is performed contemporaneously within each of said pair of trenches by a self-limiting process and leaves an area of non-porous silicon between said pair of porous silicon regions, thereby isolating said pair of adjacent trenches.

20. The self-limiting method of claim 19 wherein said forming of a pair of adjacent trenches comprises etching of said pair of adjacent trenches in said silicon substrate.

21. The self-limiting method of claim 20 wherein said etching comprises reactive ion etching.

22. The self-limiting method of claim 19 wherein said silicon substrate comprises p+ silicon.

23. The self-limiting method of claim 19 further comprising:

forming a conformal layer of a dielectric material overlying said porous silicon regions surrounding each of said adjacent trenches; and

forming a conformal layer of silicon overlying each of said conformal layers of dielectric material;

wherein for each of said adjacent trenches, said porous silicon region forms a first plate of a capacitor structure and said conformal layer of silicon forms a second plate of a capacitor structure, said first plate separated from said second plate by said conformal layer of dielectric material.

24. The self-limiting method of claim 23 wherein said dielectric material comprises a multi-layer dielectric material.

25. The self-limiting method of claim 23 wherein said dielectric material is selected from the group consisting of nitride, oxide, oxide/nitride, nitride/oxide, and oxide/nitride/oxide.

26. The self-limiting method of claim 23 wherein said conformal layer of silicon comprises polysilicon.

27. The self-limiting method of claim 23 wherein said forming of said conformal layer of dielectric material comprises deposition of said conformal layer of dielectric material.

28. The self-limiting method of claim 27 wherein said deposition comprises chemical vapor deposition.

29. The self-limiting method of claim 29 wherein said forming of said conformal layer of silicon comprises deposition of said conformal layer of silicon.

30. The self-limiting method of claim 29 wherein said deposition comprises chemical vapor deposition.