Method of making a precision capacitor array

• US 5,635,421 A
• Filed: 06/15/1995
• Issued: 06/03/1997
• Est. Priority Date: 06/15/1995
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ting, Jyh-Kang
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/490,856
• Time in Patent Office: 719 Days
• Field of Search: 437/43, 437/48, 437/52, 437/60, 437/229, 437/919, 437/233, 257/532, 156/643
• US Class Current: 438/396
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance
• CPC Class Codes: Y10S 438/941 Loading effect mitigation

Abstract

Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.

Claims

1. A method for manufacturing a precision capacitor array as part of a silicon integrated circuit comprising:

providing a layer of field oxide on a silicon substrate;

depositing a first layer of polycrystalline silicon on said layer of field oxide;

depositing a dielectric layer on said first layer of polycrystalline silicon;

depositing a second layer of polycrystalline silicon on said dielectric layer;

forming, through photolithography, a photoresist mask that defines an array of upper electrodes and a plurality of microload relief electrodes positioned on the periphery of said array wherein each of said microload relief electrodes is narrower than the upper electrodes, their distance from said array being equal to the distance between upper electrodes inside the array and their width being between about 2 and about 5 microns;

etching said second layer of polycrystalline silicon down to the level of the dielectric layer;

stripping away said photoresist mask;

depositing a passivation layer over said upper electrodes and said microload relief electrodes;

etching via holes through said passivation layer so as to expose the surface of said upper electrodes;

depositing a conductive layer over said passivation layer thereby electrically contacting said upper electrodes at the bottom of said via holes; and

patterning said conductive layer into individual conductors that connect said upper electrodes.

2. The method described in claim 1 wherein said dielectric layer comprises a material taken from the group consisting of silicon oxide, aluminum oxide, and barium titanate.

3. The method of claim 1 wherein said first and second layers of polycrystalline silicon are deposited by means of chemical vapor deposition.

4. The method of claim 1 wherein said dielectric layer is deposited by means of chemical vapor deposition.

5. The method of claim 1 wherein the etching of said second layer of polycrystalline silicon comprises dry etching and immersion in hydrofluoric acid for between about 3 and about 5 minutes at a temperature between about 20°

and about 30°

C.

6. The method of claim 1 further comprising connecting said upper electrodes to other components of said silicon integrated circuit so as to form an analog-to-digital converter.

7. The method of claim 1 further comprising connecting said upper electrodes to other components of said silicon integrated circuit so as to form a digital-to-analog converter.