Simplified dual damascene process for multi-level metallization and interconnection structure

• US 5,635,423 A
• Filed: 10/11/1994
• Issued: 06/03/1997
• Est. Priority Date: 10/11/1994
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hui, Angela, Cheung, Robin, Lin, Ming-Ren, Chang, Mark, Huang, Richard J.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/320,516
• Time in Patent Office: 966 Days
• Field of Search: 437/195, 437/190, 437/182, 437/203, 156/DIG. 652.1, 156/DIG. 653.1
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch

Abstract

A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

Claims

1. A method of forming a conductive wiring and a via on a substrate comprising:

(a) forming a first insulative layer on said substrate;

(b) forming an etch stop layer on said first insulative layer;

(c) forming a second insulative layer on said etch stop layer;

(d) forming an opening in said second insulative layer at a first location where said via is desired, said opening penetrating through said second insulative layer substantially up to but not into said etch stop layer;

(e) forming a trench in said second insulative layer at a second location where said wiring is desired while simultaneously extending said opening through said etch stop layer and through said first insulative layer wherein said trench is wider than and entirely inclusive of said opening; and

(f) simultaneously depositing a conductive material in said opening and in said trench so that said conductive material completely fills said opening and said trench, said trench forming said conductive wiring, said opening in said etch stop layer and said first insulative layer forming a conductive via, said conductive via providing electrical connection between said conductive wiring and said substrate.

2. The method recited in claim 1, wherein the first insulative layer and second insulative layer are oxide layers.

3. The method recited in claim 1, wherein said etch stop layer comprises a material selected from the group consisting if silicon nitride, silicon oxynitride and polysilicon, and said first and second insulative layers are silicon oxide.

4. The method as recited in claim 1, further comprising the step of forming a first patterned mask having a first mask opening over said second insulative layer in registry with the first location prior to forming the opening in the second insulative layer.

5. The method as recited in claim 4, further comprising the step of removing said first mask and providing a second mask having a second opening over said second insulative layer in registry with the second location prior to forming said trench in said second insulative layer and simultaneously forming said via through said etch stop layer and said first insulative layer.

6. The method as recited in claim 1, wherein the step of forming said opening in said second insulative layer is achieved by a first etching process.

7. The method as recited in claim 6, wherein the step of forming a trench in the second insulative layer while simultaneously forming a via in said etch stop layer and in said first insulative layer is achieved by a second etching process.

8. The method as recited in claim 7, wherein the first etching process and the second etching process are plasma etching processes.

9. The method as recited in claim 7, wherein the first etching process and the second etching process are reactive ion etching processes.

10. The method as recited in claim 9, wherein said first etching process has a higher selectivity with respect to the etch stop layer than said second etching process.

11. The method as recited in claim 10, further comprising the step of polishing the second insulative layer to planarize said conductive wiring and said second insulative layer.

12. The method as recited in claim 11, wherein the step of polishing is achieved by chemical-mechanical polishing.

13. The method as recited in claim 11, wherein the said conductive material comprises a metal with or without an adhesion/barrier layer, said metal selected from the group consisting of aluminum, tungsten, copper and alloys thereof.