Power semiconductor module and circuit arrangement comprising at least two power semiconductor switch modules

• US 5,635,757 A
• Filed: 02/21/1995
• Issued: 06/03/1997
• Est. Priority Date: 02/21/1994
• Status: Expired due to Fees

• Current Assignee: Asea Brown Boveri AG (ABB Limited)
• Original Assignee: Asea Brown Boveri AG (ABB Limited)
• Inventors: Stockmeier, Thomas, Thiemann, Uwe
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): ARROYO, TERESA M
• Application Number:
  US08/390,999
• Time in Patent Office: 833 Days
• Field of Search: 257/691, 257/723, 257/728, 257/678, 257/714, 257/724, 257/685, 257/167, 257/177, 257/182
• US Class Current: 257/691
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 7/20927 Liquid coolant without phase change

Abstract

A circuit arrangement and a power semiconductor module are provided in which the circuit arrangement comprises a plurality of parallel-connected power semiconductor modules, of which only one is connected to a control device. The other modules function as slaves of the master connected to the control device and draw the signal required for triggering from the master via a signal bus. For this purpose, the power semiconductor modules have a number of signal connections which are interconnected. The signal connections may be connected signalwise to the gate connections, for example via an interface. The power semiconductor modules according to the invention provide a circuit arrangement in which a plurality of modules can be connected in parallel up to maximum performances without limitations.

Claims

1. A circuit arrangement comprising at least two power semiconductor modules which each comprise:

a package, at least two main connections, and at least one gate connection for triggering and monitoring the power semiconductor modules, wherein

only one, freely selectable power semiconductor module is connected to a control device via its gate connection,

each module comprises a plurality of signal connections, the signal connections of all power semiconductor modules being interconnected and thereby forming a common signal bus driven by said module whose gate connection is connected to the control unit.

2. The circuit arrangement as claimed in claim 1, wherein the gate connection of each module comprises a first connection provided for signals to be conducted to the module and a second connection for signals to be conducted away from the module, which second and first connections are designed, in particular, as optical waveguide connections and are connected via an optical waveguide to the control device.

3. A circuit arrangement as claimed in claim 1, wherein the signal connections comprise, in particular:

a first path for triggering the switches of the power semiconductor modules;

a second path for fault signals of the power semiconductor modules;

a third path for clocking the power semiconductor modules; and

a fourth path via which all the gate electrodes of the switches of the power semiconductor modules can be connected.

4. The circuit arrangement as claimed in claim 1, wherein an interface is provided in every module between the gate connections and the signal connections.

5. The circuit arrangement as claimed in claim 1, wherein an interface between the gate connections and the signal connections is provided only in the module connected to the control device.

6. The circuit arrangement as claimed in claim 2, wherein the main connections are disposed on a first side, the signal connections on a second side and the optical waveguide connections on a third side of the package.

7. A circuit arrangement as claimed in claim 2, wherein the signal connections comprise, in particular:

a first path for triggering the switches of the power semiconductor modules;

a second path for fault signals of the power semiconductor modules;

a third path for clocking the power semiconductor modules; and

a fourth path via which all the gate electrodes of the switches of the power semiconductor modules can be connected.

8. The circuit arrangement as claimed in claim 2, wherein an interface is provided in every module between the gate connections and the signal connections.

9. The circuit arrangement as claimed in claim 2, wherein an interface between the gate connections and the signal connections is provided only in the module connected to the control device.

10. The circuit arrangement as claimed in claim 6, wherein

a) the packages are mounted on a heat sink, a coolant flows through the heat sink, coolant inlets and outlets are provided on the third side of the package.

11. A circuit arrangement as claimed in claim 6, wherein the signal connections comprise, in particular:

a first path for triggering the switches of the power semiconductor modules;

a second path for fault signals of the power semiconductor modules;

a third path for clocking the power semiconductor modules; and

a fourth path via which all the gate electrodes of the switches of the power semiconductor modules can be connected.

12. The circuit arrangement as claimed in claim 6, wherein an interface is provided in every module between the gate connections and the signal connections.

13. A circuit arrangement as claimed in claim 10, wherein the signal connections comprise, in particular:

a first path for triggering the switches of the power semiconductor modules;

a second path for fault signals of the power semiconductor modules;

a third path for clocking the power semiconductor modules; and

a fourth path via which all the gate electrodes of the switches of the power semiconductor modules can be connected.

14. The circuit arrangement as claimed in claim 10, wherein an interface is provided in every module between the gate connections and the signal connections.

15. The circuit arrangement as claimed in claim 3, wherein an interface is provided in every module between the gate connections and the signal connections.

16. A power semiconductor module comprising:

a package, at least two main connections, and at least one gate connection for triggering and monitoring the power semiconductor module wherein

a plurality of signal connections which are connected signalwise to the gate connection, and wherein

the main connections are disposed on a first side, the signal connections on a second side and the gate connections on a third side of the package.

17. The power semiconductor module as claimed in claim 16, wherein

the packages are mounted on a heat sink,

a coolant flows through the heat sink,

coolant inlets and outlets are provided on the third side of the package.

18. The power semiconductor module as claimed in claim 17, wherein the signal connections comprise, in particular:

a first path for triggering the switches of the power semiconductor modules;

a second path for fault signals of the power semiconductor modules;

a third path for clocking the power semiconductor modules; and

a fourth path via which all the gate electrodes of the switches of the power semiconductor modules can be connected.

19. The power semiconductor module as claimed in claim 18, wherein an interface is provided between the gate connections and the signal connections.