High-speed block id encoder circuit using dynamic logic

• US 5,635,862 A
• Filed: 12/29/1995
• Issued: 06/03/1997
• Est. Priority Date: 12/29/1995
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Agapiev, Borislav, Abramson, Jeffrey M., Conley, Bryon G.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/580,656
• Time in Patent Office: 522 Days
• Field of Search: 326/21, 326/62, 326/59-60, 326/105, 326/93, 341/102
• US Class Current: 326/105
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses

Abstract

A high-speed block id encoder circuit using dynamic logic includes a plurality of input signal lines received from a memory array and a plurality of output signal lines. A first portion of the encoder circuit pre-charges the plurality of output signal lines to a first state. A plurality of transistors coupled together in a single level receives the input signals and discharges the appropriate output signal lines to a second state based on the input signals. The signals produced on the output lines provide an encoded output identifying which one of the plurality of input signal lines is asserted.

Claims

1. A high-speed block identifier encoder circuit comprising:

a plurality of output signal lines for providing an encoded output identifying which one of a plurality of input signals from an array is asserted;

a first portion coupled to the plurality of output signal lines for pre-charging the plurality of output signal lines to a first state; and

a plurality of transistors coupled together in a single level for receiving the plurality of input signals and for discharging the plurality of output signal lines to a second state based on the plurality of input signals.

2. The encoder circuit of claim 1, wherein the first portion comprises:

a plurality of transistors each having a first terminal coupled to one of the plurality of output signal lines, a second terminal coupled to a voltage source, and a gate terminal coupled to a clock signal.

3. A method for generating an encoded block id identifying which one of a plurality of signals input from an array is asserted, the method comprising the steps of:

(a) receiving a clock signal;

(b) pre-charging a plurality of output signal lines to a first state when the clock signal is in a second state;

(c) receiving a first signal of the plurality of input signals after the clock signal transitions to a third state;

(d) discharging a first set of the plurality of output signal lines to a fourth state in response to the first signal; and

(e) providing the plurality of output signal lines as the encoded block id.

4. The method of claim 3, further comprising the steps of:

(f) discharging a valid output signal line to the fourth state in response to the first signal; and

(g) providing the valid output signal line in the fourth state as a valid signal indicating the encoded block id is valid on the plurality of output signal lines.

5. The method of claim 3, wherein each output signal line of the first set is coupled to a transistor of a set of transistors, wherein each transistor of the set of transistors has a gate terminal coupled to the first signal, and wherein the discharging step (d) comprises discharging the first set of lines through the set of transistors responsive to the first signal being asserted.

6. An apparatus for encoding onto a plurality of output signal lines which one of a plurality of signal lines input from an array is asserted, the apparatus comprising:

a plurality of output signal lines for providing an encoded output identifying which one of the plurality of input signals is asserted;

a clock signal input line coupled to the plurality of output signal lines through a first plurality of transistors for pre-charging the plurality of output signal lines to a first state;

a second plurality of transistors coupled together in a first level, wherein a gate terminal of each of the second plurality of transistors is coupled to one of the plurality of input signal lines; and

the second plurality of transistors for discharging the plurality of output signal lines to a second state responsive to the plurality of input signal lines.

7. The apparatus of claim 6, wherein each of the first plurality of transistors is a PMOS transistor and each of the second plurality of transistors is an NMOS transistor.

8. The apparatus of claim 6, wherein the first state corresponds to a logical one and the second state corresponds to a logical zero.

9. The apparatus of claim 6, wherein each of the second plurality of transistors is connected to only one of the plurality of input signal lines and only one of the plurality of output signal lines.

10. The apparatus of claim 9, further comprising each of the second plurality of transistors being coupled together in series with one of a third plurality of transistors, wherein a gate terminal of each of the third plurality of transistors is coupled to the clock signal input line.

11. The apparatus of claim 6, wherein the second plurality of transistors are arranged into a plurality of sets, wherein the gate terminal of each transistor of each set of the plurality of sets is coupled to one of the plurality of input signal lines, and wherein a first terminal of each transistor of a set of the plurality of sets is coupled to a different one of a subset of the plurality of output signal lines.

12. An apparatus for generating an encoded block id that identifies which one of a plurality of signals input from a memory array is asserted, the apparatus comprising:

means for receiving a clock signal;

means for pre-charging a plurality of output signal lines to a first state when the clock signal is in second first state;

means for receiving a first signal of the plurality of input signals after the clock signal transitions to a third state;

means for discharging a first set of the plurality of output signal lines to a fourth state in response to the first signal; and

means for providing the plurality of output signal lines as the encoded block id.

13. The apparatus of claim 12, further comprising:

means for discharging a valid output signal line to the fourth state in response to the first signal; and

means for providing the valid output signal line in the fourth state as a valid signal indicating the encoded block id is valid on the plurality of output signal lines.

14. The apparatus of claim 12, wherein each output signal line of the first set is coupled to a transistor of a set of transistors, wherein each transistor of the set of transistors has a gate terminal coupled to the first signal, and wherein the means for discharging comprises means for discharging the first set of lines through the set of transistors responsive to the first signal being asserted.