Comparator circuit

• US 5,635,864 A
• Filed: 06/07/1995
• Issued: 06/03/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Jones, Anthony M.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/480,997
• Time in Patent Office: 727 Days
• Field of Search: 327/77-79, 327/63, 327/91, 327/215, 327/337, 327/554, 327/560-563
• US Class Current: 327/77
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/2764 Circuits therefore
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0061 remodulation
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0073 Detection of synchronisation state
• CPC Class Codes: H04L 2027/0081 between loops of different bandwidths
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3809 Amplitude regulation arrangements
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/211 : Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/4446 : IF amplifier circuits specially adapted for B&W TV RF amplifiers in general H03F3/189
• CPC Class Codes: H04N 5/455 : Demodulation-circuits
• CPC Class Codes: H04N 5/52 : Automatic gain control

Abstract

A high speed analog-to-digital converter employs a comparator having first and second units cross coupled in a positive feedback loop. The units are alternately connected to an input voltage and a reference voltage, after which positive feedback is introduced established, and a differential output established. The arrangement is fully symmetric, and balanced and rejects common-mode switching noise.

Claims

1. An analog-to-digital converter apparatus, comprising a comparator having first and second units, each of said units comprising:

a capacitor connected to a first node and a second node;

a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage;

an inverter having an input connected to said second node, and an output; and

a second switch means for connecting said output of said inverter to said second node of an other of said units.

2. The apparatus according to claim 1, wherein each said unit further comprises a third switch means for connecting said second node and said output of said inverter.

3. The apparatus according to claim 2, wherein said inverter, said first switch means, said second switch means, and said third switch means comprise MOS transistors.

4. A comparator having first and second units, each of said units comprising:

a capacitor connected to a first node and a second node;

a first switch means for connecting said first node to a selected one of an input voltage and a reference voltage;

an inverter having an input connected to said second node, and an output; and

a second switch means for connecting said output of said inverter to said second node of an other of said units.

5. The comparator according to claim 4, wherein each said unit further comprises a third switch means for connecting said second node and said output of said inverter.

6. The comparator according to claim 5, wherein said inverter, said first switch means, said second switch means, and said third switch means comprise MOS transistors.

7. The comparator according to claim 4, wherein said capacitor, said inverter, said first switch means, and said second switch means are integrated in a CMOS integrated circuit.

8. A method of comparing two voltages, comprising in each of two associated units the steps of:

connecting a capacitor to a first node and a second node;

connecting an input of an inverter to said second node;

in a first phase of operation;

connecting said first node to a selected one of an input voltage and a reference voltage;

in a second phase of operation;

disconnecting said first node from said selected one of said input voltage and said reference voltage; and

connecting said first node to another of said input voltage and said reference voltage; and

in a third phase of operation;

disconnecting said first node from said other of said input voltage and said reference voltage; and

connecting said output of said inverter to said second node of an other of said associated units.

9. The method according to claim 8, wherein said first and second units are integrated in a semiconductor integrated circuit.

10. The method according to claim 9, wherein said integrated circuit is a CMOS circuit.

11. The method according to claim 8, further comprising the steps of:

in said first phase of operation;

connecting said input of said inverter to an output thereof; and

in said second phase of operation;

disconnecting said input of said inverter from said output thereof.

12. The method according to claim 11, wherein said first and second units are integrated in a semiconductor integrated circuit.

13. The method according to claim 12, wherein said integrated circuit is a CMOS circuit.