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Computer implemented method for producing optimized cell placement for integrated circiut chip

  • US 5,636,125 A
  • Filed: 11/13/1995
  • Issued: 06/03/1997
  • Est. Priority Date: 04/19/1994
  • Status: Expired due to Term
First Claim
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1. A computer implemented method for producing an optimized cell placement for an integrated circuit chip, comprising the steps of:

  • (a) decomposing a placement optimization methodology into a plurality of cell placement optimization processes;

    (b) performing said optimization processes simultaneously on input data representing said chip;

    (c) recomposing results of said optimization processes and producing an optimized cell placement corresponding thereto;

    (d) analyzing a fitness of said optimized cell placement;

    (e) selectively repeating performing said optimization processes for further optimizing said optimized cell placement if said fitness does not satisfy a predetermined criterion;

    (f) identifying low fitness areas of said optimized placement; and

    (g) selectively repeating performing said optimization processes on said low fitness areas respectively.

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