Semiconductor memory device having low power self refresh and burn-in functions

• US 5,636,171 A
• Filed: 12/29/1995
• Issued: 06/03/1997
• Est. Priority Date: 06/04/1994
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Haq, Ejaz Ul, Yoo, Seung-Moon
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/580,645
• Time in Patent Office: 522 Days
• Field of Search: 365/222, 365/230.06, 365/230.08
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device capable of executing a self-refresh operation to achieve a low power consumption, and of executing a burn-in operation in wafer and package states as well. A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a word line being arranged in each row to select the rows of the plurality of memory cells in response to an input of row address, a bit line being arranged in each column to select the columns of the plurality of memory cells in response to an input of column address, and the row address for designating a row accessed in a previous selection operation upon selection of an arbitrary word line comprising a controller for executing the arbitrary word line selection.

Claims

1. A semiconductor memory device having an oscillator which outputs a preset oscillating clock, and a plurality of row decoders which are selected in response to a combination input of a row address, said semiconductor memory device comprising:

a first row decoder comprising;

a first input stage, after being precharged by inputs of a precharge signal and combination signals of a decoded row address, for discharging a first connection node as an output node in response to a first combination input of said decoded row address,

a first latch circuit arranged between said first connection node and a given second connection node for latching and generating an output signal of said first input stage, and

a first driver circuit arranged between said second connection node and a first word line for amplifying and generating an output signal of said first latch circuit;

a second row decoder comprising;

a second input stage, after being precharged by inputs of the precharge signal and the combination signals of a decoded row address, for discharging a third connection node as an output node in response to a second combination input of said decoded row address,

a second latch circuit arranged between said third connection node and a given fourth connection node for latching and generating an output signal of said second input stage, and

a second driver circuit arranged between said fourth connection node and a second word line for amplifying and generating an output signal of said second latch circuit; and

a carry generator arranged between said second connection node and said third connection node for outputting a carry corresponding to a voltage level of said second connection node to said third connection node in response to a control input of an oscillating clock, thereby suppressing power consumption during a self-refresh operation by selecting said second word line using said carry.

2. The semiconductor memory device as claimed in claim 1, wherein said carry generator comprises:

a first switching transistor having one terminal being connected to said second connection node to be switched in response to the control input of said oscillating clock;

a second switching transistor having one terminal being connected to a terminal of a ground voltage and a gate being connected to a channel of said first switching transistor; and

a third switching transistor serially connected between a channel of said second switching transistor and said third connection node to be switched in response to the control input of said oscillating clock.

3. A self-refresh method of a semiconductor memory device, comprising the steps of:

sensing a self-refresh mode;

generating an address by a counter upon initiation of said self-refresh mode;

selecting a first word line to be refreshed through a first row decoder by using an output of said counter;

executing a refresh operation for memory cells connected to said first word line;

generating a carry in response to selection of said first word line and said refresh operation;

latching said carry to a second row decoder; and

executing said refresh operation for a second word line different from said first word line through the latched carry.

4. A self-refresh method of a semiconductor memory device including a memory cell array having a plurality of memory cells in rows and columns, said method comprising the steps of:

selecting a first word line connected to a row of a first memory cell arranged in the row direction using a first word line driver and a first combination input of a row address by a first row decoder;

selecting a second word line connected to a row of a second memory cell arranged in the row direction using a second word line driver using a second combination input of a row address by a second row decoder;

controlling a driving of said second word line driver using an output of said first row decoder as a carry in response to an input of a given control signal, a carry generator having an input terminal connected to an output terminal of said first row decoder and an output terminal connected to an output terminal of said second row decoder; and

upon a self-refresh operation, completing said second word line selection using said carry.