Method and apparatus for transferring data in a storage device including a dual-port buffer

• US 5,636,358 A
• Filed: 03/24/1994
• Issued: 06/03/1997
• Est. Priority Date: 09/27/1991
• Status: Expired due to Term

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Hohenstein, Gerald L., Brant, William A.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/217,126
• Time in Patent Office: 1,167 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400, 395/425, 395/440, 395/441, 395/458, 395/476, 395/444, 395/872, 395/873, 395/250
• US Class Current: 711/117
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements

Abstract

A computer storage system having a dual port buffer memory for improved performance. The invention comprises a computer storage subsystem that includes a dual port buffer memory that effectively provides two internal data busses for the storage subsystem: one bus for data transfers between the dual port buffer memory and the storage units, and a second bus for data transfers between the dual port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. In alternative configurations, the invention may use a plurality of dual port buffer memories in parallel to increase the effective throughput of the storage subsystem, and better match the bandwidth of the two busses.

Claims

1. A data storage subsystem, comprising:

a processor interface for coupling said data storage subsystem to a computer processor;

a redundant array of storage units for redundantly storing data, such that said redundant array provides protection against a loss of data;

a storage unit interface;

a subsystem processor for controlling operation of said data storage subsystem;

a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface;

wherein data transfers by said first and second ports are allowed to be concurrent and are controlled by said subsystem processor;

wherein data transfers by said first and second ports are substantially independent of each other;

wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed;

first, second, third, and fourth bus branches;

first, second, and third bus switches controlled by said subsystem processor;

a first series connection comprising said first bus branch, said first bus switch, and said second bus branch interconnecting said first port of said dual-port buffer memory and said processor interface;

a second series connection comprising said first bus branch, said second bus switch and, and said third bus branch interconnecting said system processor and said processor interface;

a third series connection comprising said third bus branch, said third bus switch, and said fourth bus branch interconnecting said system processor and said storage unit interface; and

a fourth connection comprising said fourth bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.

2. The data storage subsystem of claim 1 wherein said dual-port buffer memory is a video dynamic random access (VDRAM) memory.

3. The data storage subsystem of claim 2 wherein said first port of said VDRAM includes a shift register for transferring data into and out of said VDRAM.

4. A computer system, comprising:

a computer processor;

a processor interface;

a computer bus interconnecting said computer processor and said processor interface;

a redundant array of storage units for redundantly storing data, such that said redundant array provides protection against a loss of data;

a storage unit interface;

a subsystem processor;

a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface;

wherein data transfers through said first and second ports are allowed to be concurrent and are controlled by said subsystem processor;

wherein data transfers through said first and second ports are substantially independent of each other;

wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed;

first, second, third, and fourth bus branches;

first, second, and third bus switches controlled by said subsystem processor;

a first series connection comprising said first bus branch, said first bus switch, and said second bus branch interconnecting said first port of said dual-port buffer memory and said processor interface;

a second series connection comprising said first bus branch, said second bus switch and, and said third bus branch interconnecting said system processor and said processor interface;

a third series connection comprising said third bus branch, said third bus switch, and said fourth bus branch interconnecting said system processor and said storage unit interface; and

a fourth connection comprising said fourth bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.

5. The computer system of claim 4 wherein said dual-port buffer memory is a video dynamic random access (VDRAM) memory.

6. The computer system of claim 5 wherein said first port of said VDRAM includes a shift register for transferring data into and out of said VDRAM.

7. A method ensuring that data does not cross the same data bus twice when data is written from a computer processor to a redundant array of storage units, or when data is read from said redundant array of storage units, the method comprising the steps of:

providing a processor interface that is coupled to said computer processor by way of a data bus;

providing a redundant array of storage units for redundantly storing data, such that protection is provided against loss of data;

providing a storage unit interface;

providing a subsystem processor;

providing a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface;

wherein data transfers through said first and second ports are allowed to be concurrent and are controlled by said subsystem processor;

wherein data transfers through said first and second ports are substantially independent of each other;

wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed;

providing first, second, third, and fourth data bus branches;

providing first, second, and third bus switches that are controlled by said subsystem processor;

providing a first series connection comprising said first data bus branch, said first bus switch, and said second data bus branch interconnecting said first port of said dual-port buffer memory and said processor interface;

providing a second series connection comprising said first data bus branch, said second bus switch and, and said third data bus branch interconnecting said system processor and said processor interface;

providing a third series connection comprising said third data bus branch, said third bus switch, and said fourth data bus branch interconnecting said system processor and said storage unit interface; and

providing a fourth connection comprising said fourth data bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.