Method for interconnecting semiconductor chips in three dimensions, and component resulting therefrom
First Claim
Patent Images
1. Method for interconnecting wafers in three dimensions, the wafers comprising one or more semiconductor chips, the chips comprising pads for interconnecting them, the process being characterized by the fact that it comprises the following steps in succession:
- connecting leads (F) to the pads (Pc) of the wafers;
stacking the wafers (P);
embedding the stack by means of a selectively removable material;
treating the faces of the stack in order to reveal the leads;
forming connections (Cx) on the faces of the stack, for interconnecting the leads;
removing the selectively removable material.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and component resulting from interconnecting wafers in three dimensions, where the wafers include chips and the chips include pads. Steps in the method include connecting leads to the pads; stacking the wafers; embedding the stack by a selectively removable material; treating faces of the stack in order to reveal the leads; forming connections on the faces of the stack for interconnecting the leads; and removing the selectively removable material.
218 Citations
21 Claims
-
1. Method for interconnecting wafers in three dimensions, the wafers comprising one or more semiconductor chips, the chips comprising pads for interconnecting them, the process being characterized by the fact that it comprises the following steps in succession:
-
connecting leads (F) to the pads (Pc) of the wafers; stacking the wafers (P); embedding the stack by means of a selectively removable material; treating the faces of the stack in order to reveal the leads; forming connections (Cx) on the faces of the stack, for interconnecting the leads; removing the selectively removable material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A self-supporting component comprising:
-
a wafer stack comprising, a first wafer comprising, a first chip comprising a first pad, and a first chip carrier configured to support said first chip, and a second wafer disposed over said first wafer, comprising, a second chip comprising a second pad, and a second chip carrier configured to support said second chip, and wherein said wafer stack has a face surface; a first lead connected to the first pad and extending to said face surface of said wafer stack; a second lead connected to the second pad and extending to said face surface of said wafer stack; and a connector arranged on the face surface of the wafer stack and interconnecting said first lead and second lead, said connector configured to structurally support said wafer stack, whereby said component is made self-supporting by said connection of said first lead and said second lead to said wafer stack and by said connector interconnecting said first and the second lead.
-
-
21. A self-supporting component comprising:
-
a wafer stack comprising, a first wafer comprising, a first chip comprising a first pad, and a second wafer disposed over said first wafer, comprising, a second chip comprising a second pad; a first lead connected to the first pad and extending to said face surface of said wafer stack; a second lead connected to the second pad and extending to said face surface of said wafer stack; and a connector arranged on the face surface of the wafer stack and interconnecting said first lead and second lead, said connector configured to structurally support said wafer stack, whereby said component is made self-supporting by said connection of said first lead and said second lead to said wafer stack and by said connector interconnecting said first and the second lead.
-
Specification