Efficient architecture for correcting component mismatches and circuit nonlinearities in A/D converters

• US 5,638,071 A
• Filed: 06/12/1996
• Issued: 06/10/1997
• Est. Priority Date: 09/23/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Capofreddi, Peter D., Wong, Bill C., Fong, Edison
• Primary Examiner(s): DeBoer, Todd
• Application Number:
  US08/662,273
• Time in Patent Office: 363 Days
• Field of Search: 341/116, 341/120, 341/118, 341/155
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1047 using an auxiliary digital/analogue converter for adding the correction values to the analogue signal H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.

Claims

1. A high-resolution, error-correcting analog-to-digital (A/D) conversion circuit comprising:

a core A/D converter that continuously samples an analog input signal, divides the maximum voltage range of the analog input signal into a plurality of intervals, determines which of the plurality of intervals bounds the sampled input signal, and outputs an n-bit uncorrected code that uniquely identifies the interval that bounds the sampled input signal, the n bits of the uncorrected code including a first r bits, an intermediate s bits, and a last t bits;

an offset look-up table that receives the first r bits of the n-bit uncorrected code, and outputs a x-bit offset coefficient code;

a gain look-up table that receives the first r bits of the n-bit uncorrected code, and outputs a y-bit gain coefficient code;

a plurality of mismatch look-up tables, each mismatch look-up table receiving one or more of the intermediate s bits of the n-bit uncorrected code, and outputting a z-bit mismatch coefficient code;

a plurality of mismatch multipliers which correspond with the plurality of mismatch look-up tables, each mismatch multiplier multiplying the y-bit gain coefficient code to one of the z-bit mismatch coefficient codes to produce a multiplied mismatch code;

an end bit multiplier that receives the last t bits of the n-bit uncorrected code, and multiplies the gain coefficient code to the last t bits of the uncorrected code to produce a last code; and

an adder that sums the offset coefficient code, each of the multiplied mismatch codes, and the last code to produce a corrected code.

2. The conversion circuit of claim 1 wherein each mismatch table includes a memory that stores a plurality of coefficients.

3. The conversion circuit of claim 2 wherein the coefficients compensate for component mismatch errors produced by components of the core A/D converter that produce the intermediate s bits.

4. The conversion circuit of claim 1 wherein the offset look-up table includes a memory that stores a plurality of coefficients.

5. The conversion circuit of claim 4 wherein the coefficients compensate for nonlinearity errors produced by the core A/D converter.

6. The conversion circuit of claim 1 wherein the gain look-up table includes a memory that stores a plurality of coefficients.

7. The conversion circuit of claim 6 wherein the coefficients compensate for nonlinearity errors produced by the core A/D converter.

8. The conversion circuit of claim 1 wherein the plurality of mismatch tables corresponds to the number of intermediate s bits.

9. The conversion circuit of claim 1 wherein the number of bits in the uncorrected code is greater than the number of bits in the corrected code.

10. A high-resolution, error-correcting analog-to-digital (A/D) conversion circuit comprising:

an A/D converter that continuously samples an analog input signal, divides the maximum voltage range of the analog input signal into a plurality of intervals, determines which of the plurality of intervals bounds the sampled input signal, and outputs an n-bit uncorrected code that uniquely identifies the interval that bounds the sampled input signal, the n bits of the uncorrected code including a first r bits, a first intermediate sl bits, a second intermediate s2 bits, and a last t bits;

an offset look-up table that receives the first r bits of the n-bit uncorrected code, and outputs a x-bit offset coefficient code;

a gain look-up table that receives the first r bits of the n-bit uncorrected code, and outputs a y-bit gain coefficient code;

a plurality of mismatch look-up tables, each mismatch look-up table receiving the first r bits and one or more of the first intermediate sl bits of the n-bit uncorrected code, and outputting a z-bit mismatch coefficient code;

a first multiplier that multiplies the second intermediate s2 bits of the n-bit uncorrected code to the gain coefficient to produce a variable gain code;

a second multiplier that multiplies the last t bits of the n-bit uncorrected code to a fixed gain coefficient to produce a fixed gain code; and

an adder that sums the offset coefficient code, each of the mismatch coefficient codes, the variable gain code, and the fixed gain code to produce a corrected code.

11. The conversion circuit of claim 10 wherein each mismatch table includes a memory that stores a plurality of coefficients.

12. The conversion circuit of claim 11 wherein the coefficients compensate for component mismatch errors produced by components of the core A/D converter that produce the intermediate s bits.

13. The conversion circuit of claim 10 wherein the offset look-up table includes a memory that stores a plurality of coefficients.

14. The conversion circuit of claim 13 wherein the coefficients compensate for nonlinearity errors produced by the core A/D converter.

15. The conversion circuit of claim 10 wherein the gain look-up table includes a memory that stores a plurality of coefficients.

16. The conversion circuit of claim 15 wherein the coefficients compensate for nonlinearity errors produced by the core A/D converter.

17. The conversion circuit of claim 10 wherein the plurality of mismatch tables corresponds to the number of intermediate sl bits.

18. The conversion circuit of claim 10 wherein the number of bits in the uncorrected code is greater than the number of bits in the corrected code.