Window-dependent brightness/tint control for video digital-to-analog converters

• US 5,638,090 A
• Filed: 12/01/1994
• Issued: 06/10/1997
• Est. Priority Date: 12/01/1994
• Status: Expired due to Term

• Current Assignee: Shared Memory Graphics LLC (Acacia Research Corporation)
• Original Assignee: Alliance Semiconductor Corporation
• Inventors: Schnaitter, William N., Daniel, Andrew, Greene, Spencer H.
• Primary Examiner(s): BRIER, JEFFERY A
• Application Number:
  US08/347,720
• Time in Patent Office: 922 Days
• Field of Search: 345/113-116, 345/118-120, 345/150, 345/153, 345/155, 345/211
• US Class Current: 345/419
• CPC Class Codes: G09G 1/285 Interfacing with colour displays, e.g. TV receiver
• CPC Class Codes: G09G 2320/0606 Manual adjustment
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2320/0666 for control of colour parameters, e.g. colour temperature
• CPC Class Codes: G09G 2320/0686 with two or more screen areas displaying information with different brightness or colours
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: H04N 5/57 Control of contrast or brightness
• CPC Class Codes: H04N 9/643 Hue control means, e.g. flesh tone control

Abstract

A display control circuit controls the outputs of the three video DACs of an RGB monitor on a window-to-window basis to enable the display of motion video and text on the same screen with different brightness and/or tint. A digital overdrive signal, synchronized to the video DAC digital inputs, is used to enable added DAC elements for the pixels in the video windows only. Stored digital instructions determine how many and which added DAC elements are enabled by the overdrive bit(s). By storing different instructions for each of the three video DACs, the circuit may also provide window-dependent tint control. By increasing the number of bits of digital data synchronized to the digital DAC inputs, the stored instructions may be reduced or eliminated. In this case, each of several windows may be set to differing brightness and tint levels. As many different values of brightness and tint may be available as desired by increasing the number of synchronized input enabling bits and the number and strength of the added DAC elements.

Claims

1. In a visual display system that includes a display monitor that provides a visual display and a plurality of video digital-to-analog converter networks, each video digital-to-analog converter (DAC) network having an output connected to a corresponding control input of the display monitor and being responsive to a digital pixel control input signal that determines the value of a current output signal provided by said video DAC network to the control input for each pixel of the visual display, the improvement comprising, for each video DAC network, a display control circuit for controlling brightness in a selected window of the visual display, the display control circuit comprising:

an added DAC network that responds to an enabling control signal by providing a supplemental current output signal to the monitor control input connected to receive the current output signal from the associated video DAC network;

an instruction storage register that stores instruction data that define the value of the supplemental current output signal;

a logic block that responds to the instruction data provided by the instruction storage register by generating an enabling control signal that causes the added DAC network to provide the supplemental current output signal, the logic block being enabled to provide the enabling control signal by a window-dependent overdrive input signal that is synchronous to the digital pixel control input signal and that defines the selected window of the visual display.

2. A visual display system as in claim 1 and wherein each of the display control circuits is individually controlled such that the added DAC networks are independently enabled whereby a selected window on the display can have different tint than another window on the display.

3. A visual display system as in claim 1 wherein the overdrive input signal is a multi-bit signal.

4. A visual display system as in claim 1 wherein the overdrive input signal is a single-bit signal that is common to each of the display control circuits in the system and wherein each of the display control circuits has an independent instruction storage register associated therewith whereby to allow each individual video DAC to increase its output intensity by a different amount in response to the single-bit overdrive input signal whereby a selected window on the display can have different tint than another window on the display.

5. A visual display system as in claim 4 wherein the instruction data stored in the instruction storage register is multi-bit data, and at least one bit of the multi-bit data defines the value of the supplemental current signal to be greater than zero.

6. A visual display system as in claim 1 wherein the overdrive input signal is a multi-bit signal that is common to each of the display control circuits in the system and wherein each of the display control circuits has an independent instruction storage register associated therewith whereby to allow multiple enhanced levels of brightness in different selected windows of the visual display.

7. A visual display system as in claim 1 and further comprising a user interface device connected to each of the display control circuits for selectively varying the stored instruction data whereby user implemented variations in the supplemental current output signal can be performed on the fly.

8. A visual display system as in claim 1 and further comprising, for each video DAC, brightness reduction means connected in series with the overdrive input signal for inverting the overdrive input signal whereby the brightness of the selected window can be dimmed relative to other windows on the display.

9. A display control circuit for controlling brightness in a selected window of a visual display generated by a visual display system, the visual display system including a display monitor that provides the visual display and a plurality of video digital-to-analog converter networks, each video digital-to-analog converter (DAC) network having an output connected to a corresponding control input of the display monitor and responsive to a digital pixel control signal that determines the value of a current output signal provided by the video DAC network to the control input for each pixel of the video display, the display control circuit comprising:

an added DAC network that responds to an enabling control signal by providing a supplemental current output signal to the monitor control input connected to receive the current output signal from the associated video DAC network;

an instruction storage register that stores instruction data that define the value of the supplemental current output signal;

a logic block that responds to the instruction data provided by the instruction storage register by generating an enabling control signal that causes the added DAC network to provide the supplemental current output signal, the logic block being enabled to provide the enabling control signal by a window-dependent overdrive input signal that is synchronous to the digital pixel control input signal and that defines the selected window on the visual display.

10. A display control circuit as in claim 9 wherein the overdrive input signal is a multi-bit signal.

11. A display control circuit as in claim 9 wherein the overdrive input signal is a single-bit signal that is common to the display control circuit associated with each of the plurality of video DAC networks and wherein each of the display control circuits has an independent instruction storage register associated therewith whereby to allow each individual video DAC network to increase its output intensity by a different amount in response to the single-bit overdrive input signal.

12. A display control circuit as in claim 11 wherein the instruction data stored in the instruction storage register is multi-bit data, and at least one bit of the multi-bit data defines the current value of the supplemental current signal to be greater than zero.

13. A display control circuit as in claim 9 wherein the overdrive input signal is a multi-bit signal that is common to the display control circuit associated with each of the plurality of video DACs and wherein each of the plurality of display control circuits has an independent instruction storage register associated therewith whereby to allow multiple enhanced levels of brightness in different selected windows of the visual display.

14. A visual display control system for controlling the visual display of a RGB monitor having three input control ports, the visual display control system comprising:

three video digital-to-analog converter (DAC) networks, each of the three video DAC networks having an output connected to a corresponding one of the three input control ports of the RGB monitor, each of the video DAC networks being responsive to an n-bit digital input signal which changes in synchronism to provide an n-bit digital value for each pixel of the visual display, the video DAC network being responsive to the n-bit value by providing a corresponding current signal to the corresponding input control port of the RGB monitor;

three added DAC networks, each of the added DAC networks having an output connected to a corresponding one of the three input control ports of the RGB monitor, each of the added DAC networks being responsive to a multi-bit digital input signal, independent of and unrelated to the n-bit digital input signal, by providing a corresponding supplemental current signal to the corresponding input control port of the RGB monitor; and

for each added DAC network, a logic block that, when enabled, responds to instruction data by providing a multi-bit digital input signal defined by the instruction data, the logic block being enabled by an overdrive signal that is in synchronism with the n-bit digital input signal and defines the pixels of a selected window on the display.

15. A visual display control system for controlling the visual display of a RGB monitor having three input control ports, the visual display control system comprising, for each of the three input control ports:

a video DAC network having an output connected to said input control port, the video DAC network being responsive to a multi-bit digital input signal which changes in synchronism to provide a multi-bit digital value for each pixel of the visual display, the video DAC network being responsive to the multi-bit digital value by providing a corresponding current signal to said input control port;

an added DAC network that includes a plurality of added DAC elements, each added DAC element having an output connected to said input control port, the added DAC network being responsive to a multi-bit enable signal, independent of and unrelated to the multi-bit digital input signal, that activates selected of the added DAC elements to provide a supplemental current signal to said input control port;

an instruction storage register that stores instruction data;

a logic block that is enabled by a single-bit overdrive signal that is in synchronism with the multi-bit digital input signal and that defines the pixels of a selected window of the visual display, wherein the logic block responds to the instruction data provided by the instruction storage register by providing a corresponding multi-bit enable signal.

16. A visual display control system as in claim 15 and wherein each of the instruction storage registers stores different instruction data whereby the supplemental current signal provided to each input control port is different from the supplemental current signal provided to the other two input control ports.