Separable cells having wiring channels for routing signals between surrounding cells

• US 5,638,288 A
• Filed: 08/24/1994
• Issued: 06/10/1997
• Est. Priority Date: 08/24/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Deeley, Richard
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Walker, Tyrone V.
• Application Number:
  US08/295,094
• Time in Patent Office: 1,021 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/130
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.

Claims

1. A method of routing connections between circuit blocks on an integrated circuit device, comprising:

providing an integrated circuit device having a first circuit block and a plurality of second circuit blocks;

separating the first circuit block into a plurality of sub-blocks to provide a wiring channel running between a pair of adjacent sub-blocks, such that a total size of the adjacent sub-blocks and the wiring channel is larger than a size of the first circuit block prior to separation; and

routing connections between at least two of the plurality of second circuit blocks through the wiring channel;

wherein

the adjacent sub-blocks are separated by a distance which is greater than or equal to that distance necessary to create a wiring channel large enough to accommodate the connections, and is no larger than a distance "d" which ensures that the separated first circuit block operates within performance specifications which include timing constraints.

2. The method according to claim 1, wherein the first circuit block is separated by stretching the first circuit block about a parting line.

3. The method according to claim 1, wherein:

the first circuit block is separated by splitting the first circuit block about a parting line.

4. The method according to claim 1, wherein the first circuit block is a megacell.

5. The method according to claim 1, wherein:

at least a pair of the plurality of second circuit blocks are standard cells.

6. The method according to claim 1, wherein:

the first circuit block are physically larger than the pair of second circuit blocks.

7. The method according to claim 1, wherein:

two or more wiring channels are provided through the first block.

8. The method, according to claim 1, wherein the plurality of second circuit blocks are interconnected through the wiring channels.

9. A separable megacell for integrated circuit design, comprising:

a pre-defined logic function including a plurality of circuit blocks, said pre-defined logic function having a pre-defined shape and size;

a parting line through the pre-defined logic function, said circuit blocks being partitioned within the pre-defined logic function about the parting line; and

a maximum separation distance defined for the predefined logic function by which circuit blocks on opposite sides of the parting line can be separated while continuing to meeting a pre-defined set of performance specifications for the pre-defined logic function; and

a wiring channel through the pre-defined logic function about the parting line, said wiring channel dividing the megacell into two distinct portions;

wherein;

the circuit blocks are interconnected by a plurality of signals, some of which are more timing-critical than others; and

the circuit blocks are partitioned about the parting line such that only the least timing-critical signals cross the parting line.

10. A separable megacell for integrated circuit design according to claim 9, further comprising:

a wiring channel through the pre-defined logic function about the parting line, said wiring channel dividing the megacell into two distinct portions.

11. A separable megacell for integrated circuit design according to claim 10, wherein:

the two distinct portions and the wiring channel are treated as a single logical entity.

12. A separable megacell for integrated circuit design according to claim 10, wherein:

the two distinct portions are treated as two separate logical entities, with a maximum split distance between the two portions being defined as being equal to the maximum separation distance.

13. A separable megacell for integrated circuit design according to claim 9, wherein at least two parting lines through the pre-defined logic function are oriented parallel to one another.

14. A separable megacell for integrated circuit design according to claim 9, wherein:

at least two parting lines through the pre-defined logic function are oriented along non-parallel paths.

15. A method of designing an integrated circuit, comprising the steps of:

providing a plurality of pre-defined cells;

providing a separable megacell through which a parting line passes;

separating the megacell about the parting line to form a wiring channel, such that a total size of the megacell and the wiring channel after separation of the megacell is larger than a size of the megacell prior to separation;

routing signals between at least two of the pre-defined cells through the wiring channel; and

defining a maximum separation distance about the parting line;

wherein;

the megacell is separated about the parting line by a distance less than or equal to the maximum separation distance; and

the megacell is separated about the parting line by a distance greater than or equal to that distance necessary to create a wiring channel large enough to accommodate the signals routed therethrough.

16. A method of making an integrated circuit according to claim 15, further comprising the step of treating the separated megacell and the wiring channel therethrough as a single logical entity.

17. A method of making an integrated circuit according to claim 15, further comprising the step of treating the separated megacell as two or more distinct logic entities, with the wiring channel occurring as between the two or more distinct logic entities.

18. A method of making an integrated circuit according to claim 15, further comprising the steps of:

defining at least two parting lines along substantially parallel paths through the separable megacell; and

separating the megacell about the at least two parting lines to form at least two corresponding substantially parallel wiring channels.

19. A method a making an integrated circuit according to claim 15, further comprising the steps of:

defining at least two parting lines through the separable megacell along non-parallel paths; and

separating the separable megacell about the two nonparallel parting lines to form at least two corresponding nonparallel wiring channels.

20. A method of making an integrated circuit according to claim 15, further comprising the steps of:

routing signals between the separated portions of the separable megacell in a first wiring layer; and

routing the signals which pass through the wiring channel in a least one second wiring layer, distinct from the first wiring layer.

21. A method of making an integrated circuit according to claim 20, further comprising the step of routing the signals which pass through the wiring channel in two or more second wiring layers.

22. A method of making an integrated circuit according to claim 21, further comprising the step of routing the signals in the second wiring layers in a vertically stacked configuration.

23. A method of making an integrated circuit according to claim 21, further comprising the step of routing the signals in the two or more second wiring layers in a vertically staggered configuration.

24. A method of forming connections between circuit blocks on an integrated circuit, comprising:

defining, on an integrated circuit, two first circuit blocks;

defining, on the integrated circuit, a second circuit block between the two first circuit blocks;

defining a first parting line through the second circuit block;

separating the second circuit block about the first parting line to form a first wiring channel, such that a total size of the second circuit block and the first wiring channel after separation of the second circuit block is larger than a size of the second circuit block prior to separation; and

routing signals between the two first circuit blocks through the first wiring channel;

wherein;

the first wiring channel has a width which is greater than or equal to that necessary to accommodate the connections, and is no larger than a distance "d" which ensures that the separated second circuit block operates within performance specifications which include timing constraints.

25. A method of forming connections between circuit blocks on an integrated circuit according to claim 24, further comprising:

defining at least one second parting line through the second circuit block;

separating the second circuit block about the second parting line to form a second wiring channel; and

routing signals through the second wiring channel.