Optimal pad location method for microelectronic circuit cell placement

• US 5,638,293 A
• Filed: 09/13/1994
• Issued: 06/10/1997
• Est. Priority Date: 09/13/1994
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, D'Haeseleer, Patrik
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Walker, Tyrone V.
• Application Number:
  US08/306,189
• Time in Patent Office: 1,001 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/474.35, 364/474.36
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A cell placement is generated for a microelectronic circuit chip. Interconnect points for cell nets are calculated, for example, as gravity points of the cells of the respective nets. Optimal positions for external connection terminals or pads along the border of the circuit are calculated as being the closest positions to the respective interconnect points. The total wirelength of the placement is calculated as including the distances between the interconnect points and the respective pads. Where initial location of the pads results in overlap thereof, clusters of pads are identified and expanded to remove the overlap. Concatenated overlapping clusters resulting from expansion are treated as new clusters and subsequently expanded until all overlap is eliminated. The centers of gravity of the clusters are preserved. During the overlap removal process, initial rectangular coordinates of the pad positions are converted into linear coordinates along the border. After the overlap is eliminated, the linear coordinates are converted back to rectangular coordinates.

Claims

1. A method for optimally locating a plurality of electrical terminals on a border of a microelectronic circuit that includes a plurality of cells, comprising the steps of:

(a) performing a placement of said cells;

(b) calculating cell interconnect points in said placement corresponding to the electrical terminals respectively;

(c) calculating positions on said border at which distances between said positions and said interconnect points are minimum respectively; and

(d) locating the terminals at said positions respectively, in which;

step (c) enables said positions to be calculated such that the terminals can overlap after performing step (d); and

the method further comprises the steps, performed after step (d), of;

(e) calculating adjusted positions for said terminals respectively in accordance with a predetermined function such that said overlap is eliminated; and

(f) locating the terminals at said adjusted positions respectively;

step (c) comprises calculating said positions in two-dimensional coordinates respectively; and

step (e) comprises the substeps of;

(g) converting said positions into one-dimensional coordinates measured along said border respectively;

(h) calculating said adjusted positions in one-dimensional coordinates; and

(i) converting said adjusted positions into two-dimensional coordinates.

2. A method for optimally locating a plurality of electrical terminals on a border of a microelectronic circuit that includes a plurality of cells, comprising the steps of:

(a) performing a placement of said cells;

(b) calculating cell interconnect points in said placement corresponding to the electrical terminals respectively;

(c) calculating positions on said border at which distances between said positions and said interconnect points are minimum respectively; and

(d) locating the terminals at said positions respectively, in which;

step (c) enables said positions to be calculated such that the terminals can overlap after performing step (d); and

the method further comprises the steps, performed after step (d), of;

(e) calculating adjusted positions for said terminals respectively in accordance With a predetermined function such that said overlap is eliminated; and

(f) locating the terminals at said adjusted positions respectively;

step (c) comprises calculating said positions in rectangular coordinates respectively; and

step (e) comprises the substeps of;

(g) converting said positions into linear coordinates measured along said border respectively;

(h) calculating said adjusted positions in linear coordinates; and

(i) converting said adjusted positions into rectangular coordinates.

3. A method for removing overlap between electrical terminals on a border of a microelectronic circuit resulting from initial location of the terminals at positions that allow said overlap, comprising the steps of:

(a) identifying overlapping clusters of terminals;

(b) calculating adjusted positions for said terminals of said clusters respectively in accordance with a predetermined function such that said overlap is eliminated; and

(c) locating the terminals at said adjusted positions respectively, in which;

said positions are specified in two-dimensional coordinates prior to performing step (a) respectively; and

step (b) comprises the substeps of;

(d) converting said positions into one-dimensional coordinates measured along said border respectively;

(e) calculating said adjusted positions in one-dimensional coordinates; and

(f) converting said adjusted positions into two-dimensional coordinates.

4. A method as in claim 3, in which step (b) comprises calculating said adjusted positions such that centers of gravity of said clusters of terminals after performing step (c) are substantially the same as said centers of gravity of said clusters of terminals before performing step (a).

5. A method as in claim 3, in which:

said clusters of terminals can be concatenated to form overlapping new clusters of terminals after performing step (c); and

the method further comprises the steps, performed after step (c), of;

(g) identifying said new overlapping clusters of terminals; and

(h) calculating new adjusted positions to expand said new clusters of terminals.

6. A method for removing overlap between electrical terminals on a border of a microelectronic circuit resulting from initial location of the terminals at positions that allow said overlap, comprising the steps of:

(a) identifying overlapping clusters of terminals;

(b) calculating adjusted positions for said terminals of said clusters respectively in accordance with a predetermined function such that said overlap is eliminated; and

(c) locating the terminals at said adjusted positions respectively, in which;

said positions are specified in rectangular coordinates prior to performing step (a) respectively; and

step (b) comprises the substeps of;

(d) converting said positions into linear coordinates measured along said border respectively;

(e) calculating said adjusted positions in linear coordinates; and

(f) converting said adjusted positions into rectangular coordinates.

7. A method as in claim 6, in which step (b) further comprises the substep, performed between steps (d) and (e), of:

(g) sorting said positions in accordance with said linear coordinates thereof.