Hierarchical DRAM array with grouped I/O lines and high speed sensing circuit

• US 5,638,317 A
• Filed: 04/04/1994
• Issued: 06/10/1997
• Est. Priority Date: 08/22/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tran, Hiep V.
• Primary Examiner(s): GOSSAGE, GLENN A
• Application Number:
  US08/222,507
• Time in Patent Office: 1,163 Days
• Field of Search: 365/203, 365/51, 365/63, 365/205, 365/207, 365/208, 365/189.07, 365/189.05, 365/190, 365/201, 307/530, 327/51, 327/52, 327/54, 327/55
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A random access memory array architecture including a plurality of arrays or subarrays arranged into rows and columns, a plurality of sense amplifiers between the arrays (2), and grouped input/output (I/O) lines. The I/O path includes main I/O lines (24) coupled to all of the arrays, with orthogonal local I/O lines (20) for a column of arrays plus sub I/O lines (16) orthogonal to the local I/O lines for each group of sense amplifiers in a row of sense amplifiers. A plurality of pass transistor pairs and interconnect transistors are coupled to the sense amplifiers and the local and sub I/O lines. Latches are provided for storing data output from each of the subarrays, and a match comparator is connected to at least two of the latches for providing a signal on a complementary pair of match leads indicative of a comparison of the data in the latches. A true lead of the complementary pair of match leads is precharged high before the comparison while a complement lead of the complementary pair of match leads is precharged low.

Claims

1. A random access memory comprising:

a plurality of subarrays arranged into rows and columns, each subarray including;

a plurality of bit line pairs having a plurality of memory cells connected thereto;

a plurality of first sense amplifiers, at least one for each bit line pair, connected to said bit line pairs, each of said sense amplifiers having true and complement output terminals providing true and complement output signals;

a plurality of pass transistor pairs, one of said pass transistor pairs for each of said plurality of first sense amplifiers, each of said pass transistor pairs having a true pass transistor and a complement pass transistor, each of said true and complement pass transistors having a control terminal connected to receive a sense amplifier select signal, the true pass transistor having a first current handling terminal connected to the true output terminal of one of said first sense amplifiers and having a second current handling terminal, the complement pass transistor having a first current handling terminal connected to the complement output terminal of said one of said first sense amplifiers and having a second current handling terminal;

a sub I/O bus having a true lead connected to the second current handling terminals of the true pass transistors and having a complement lead connected to the second current handling terminals of the complement pass transistors;

a local I/O bus comprising true and complement leads, said local I/O bus running parallel to said bit line pairs, said true lead of said local I/O bus being connected to said true lead of said sub I/O bus via a true bus interconnect transistor, said true bus interconnect transistor having a control terminal connected to receive a subarray write selection signal, and said complement lead of said local I/O bus being connected to said complement lead of said sub I/O bus via a complement bus interconnect transistor, said complement bus interconnect transistor having a control terminal connected to receive said subarray write selection signal; and

a second sense amplifier having a first transistor, said first transistor having a control terminal connected to said true lead of said sub I/O bus, a first current handling terminal connected to said complement lead of said local I/O bus and a second current handling terminal, said second sense amplifier having a second transistor, said second transistor having a control terminal connected to said complement lead of said sub I/O bus, a first current handling terminal connected to said true lead of said local I/O bus and a second current handling terminal connected to said second current handling terminal of said first transistor, said second sense amplifier having a third transistor, said third transistor having a control terminal connected to receive a subarray read select signal, a first current handling terminal connected to the second current handling terminals of said first and second transistors, and a second current handling terminal, said second sense amplifier having a fourth transistor, said fourth transistor having a control terminal connected to receive a section select signal, a first current handling terminal connected to said second current handling terminal of said third transistor and a second current handling terminal connected to a reference potential.

2. A random access memory as in claim 1 wherein each of said first sense amplifiers comprises cross coupled inverters.

3. A random access memory as in claim 1 wherein the true and complement pass transistors of said pass transistor pairs comprise field effect transistors.

4. A random access memory as in claim 1 wherein said sub I/O bus extends perpendicularly to said bit lines.

5. A random access memory as in claim 1 wherein said true bus interconnect transistor and said complement bus interconnect transistor comprise field effect transistors.

6. A random access memory as in claim 1 wherein said first, second, third and fourth transistors of said second sense amplifier comprise field effect transistors.

7. A random access memory as in claim 1 further including a plurality of word lines running perpendicular to said bit lines, each word line being connected to one memory cell of said plurality of memory cells on each of said bit line pairs.

8. A random access memory as in claim 1 wherein said memory is a dynamic random access memory.

9. A random access memory comprising:

a memory cell array having a plurality of subarrays arranged into rows and columns;

an I/O bus having at least one complementary pair of data leads positioned between at least two of said subarrays, and having a complementary pair of match leads;

a plurality of latches, one for each of said subarrays, for storing output data from each of said subarrays, and positioned between the corresponding subarray and said I/O bus; and

a match comparator connected to at least two of said latches, said match comparator comparing data in said latches and providing a first signal on said complementary pair of match leads if the data in said latches match and a second signal if the data in said latches do not match

wherein a true lead of said complementary pair of match leads is precharged high before comparison by said comparator and a complement lead of said complementary pair of match leads is precharged low before comparison by said comparator; and

said comparator includes a first series pair of pass transistors connected between said complementary pair of match leads, a control gate of one transistor of said first series pair of pass transistors connected to a true output of a first one of said latches and a control gate of the other transistor of said first series pair of pass transistors connected to a complement output of a second one of said latches.

10. A random access memory as in claim 9 wherein

said comparator also includes a second series pair of pass transistors connected between said complementary pair of match leads, a control gate of one transistor of said section series pair of pass transistors connected to a true output of said second one of said latches and a control gate of the other transistor of said second series pair of pass transistors connected to a complement output of said first one of said latches.