High resolution analog storage EPROM and flash EPROM

• US 5,638,320 A
• Filed: 01/11/1996
• Issued: 06/10/1997
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Invoice Technology Incorporated
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/585,138
• Time in Patent Office: 516 Days
• Field of Search: 365/185.03, 365/185.19, 365/185.21
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read process determines a memory cell'"'"'s threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts. Another read process slowly ramps the source voltage of a memory cell and determines the cell'"'"'s threshold voltage from the drain voltage of the memory cell. Still another read process connects a cascoding device to a memory cell and biases the memory cell in the linear region while the threshold voltage of the memory cell is determined from a voltage across a load which carries a current that mirrors the current through the memory cell. Read processes disclosed for analog memory cells also apply to binary memory cells, multilevel digital memory cells, and other applications which require precise reading of threshold voltages.

Claims

1. A method for reading a threshold voltage of a memory cell, comprising:

connecting the memory cell, a cascoding device, and a first transistor in series between a voltage supply and ground, wherein the first transistor has a gate coupled to its drain;

biasing the memory cell in the linear region;

connecting a load and a second transistor in series between the voltage supply and ground, wherein a gate of the second transistor is connected to the gate of the first transistor so that current through the second transistor mirrors current through the first transistor; and

measuring at a first terminal of the load a voltage that indicates the threshold voltage of the memory cell.

2. The method of claim 1, wherein measuring the voltage at the first terminal of the load comprises:

generating a reference signal which indicates the threshold voltage of a reference cell which has the same structure as the memory cell;

connecting the first terminal of the load to a first input terminal of a difference amplifier;

applying the reference signal to a second input terminal of the difference amplifier; and

measuring the output voltage of the difference amplifier.

3. The method of claim 2, wherein generating the reference signal comprises:

connecting the reference cell, a second cascoding device, and a third transistor in series between the voltage supply and ground, wherein the third transistor has a gate coupled to its drain;

biasing the reference cell in the linear region; and

connecting a second load and a fourth transistor in series between the voltage supply and ground, wherein a gate of the fourth transistor is connected to the gate of the third transistor so that current through the fourth transistor mirrors current through the third transistor, wherein

a voltage at a first terminal of the second load indicates the reference signal.

4. A method for reading a threshold voltage of a memory cell, comprising:

coupling a drain/source of the memory cell through a high impedance load to a reference voltage;

applying a bias voltage to a control gate of the memory cell;

ramping a voltage of a source/drain of the memory cell from the reference voltage to the bias voltage, wherein the ramping is done at a rate which initially operates the memory cell in the linear region and prevents channel hot electrons from disturbing the threshold voltage of the memory cell; and

sensing the voltage at the drain/source to determine the threshold voltage of the memory cell.

5. The method of claim 4, further comprising applying the reference voltage to the source/drain of the memory cell for a time while applying the bias voltage to the control gate and before beginning ramping.

6. The method of claim 4, wherein sensing the voltage at the drain/source further comprises:

generating a reference signal which indicates the threshold voltage of a reference cell having the same structure as the memory cell;

connecting the drain/source to a first input terminal of a difference amplifier;

applying the reference signal to a second input terminal of the difference amplifier; and

measuring the output voltage of the difference amplifier.

7. The method of claim 6, wherein generating the reference signal comprises:

coupling a drain/source of the reference cell through a high impedance load to ground;

applying the first bias voltage to a control gate of the reference cell; and

ramping a voltage of a source/drain of the reference cell from the reference voltage to the second bias voltage, wherein the drain/source of the reference cell carries the reference signal when the source/drain is at the bias voltage.

8. A method for reading a threshold voltage of a memory cell, comprising:

ramping a control gate voltage of the memory cell between a first voltage and a second voltage;

sensing when the memory cell transitions between non-conducting and conducting; and

reading the control gate voltage when the memory cell transitions.

9. The method of claim 8, wherein ramping comprises changing the control gate voltage continuously.

10. The method of claim 8, wherein ramping comprises changing the control gate voltage in steps having a size equal to a desired resolution.

11. The method of claim 8, wherein:

the first voltage is lower than a minimum possible threshold voltage for the memory cell;

the second voltage is higher than a maximum possible threshold voltage for the memory cell; and

ramping comprises increasing the control gate voltage from the first voltage to the second voltage.

12. The method of claim 8, wherein:

the first voltage is higher than a maximum possible threshold voltage for the memory cell;

the second voltage is lower than a minimum possible threshold voltage for the memory cell; and

ramping comprises decreasing the control gate voltage from the first voltage to the second voltage.

13. The method of claim 8, further comprising:

generating a reference signal which indicates the threshold voltage of a reference cell having the same structure as the memory cell;

applying the sampled and held control gate voltage to a first input terminal of a difference amplifier;

applying the reference signal to a second input terminal of the difference amplifier; and

measuring the output voltage of the difference amplifier.

14. The method of claim 13, wherein generating the reference signal comprises:

ramping a control gate voltage of the reference cell between the first voltage and the second voltage;

sensing when the reference cell transitions between conducting and non-conducting; and

sampling and holding the control gate voltage of the reference cell when the reference cell transitions, wherein the control gate voltage when the reference cell transitions is the reference signal.