Integrated circuit I/O using a high performance bus interface

• US 5,638,334 A
• Filed: 05/24/1995
• Issued: 06/10/1997
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/448,657
• Time in Patent Office: 748 Days
• Field of Search: 365/230.03, 365/207, 365/208, 365/200, 365/205, 365/203
• US Class Current: 365/230.03
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes a memory device having a plurality of independently addressable memory sections, each of the memory sections is assigned a portion of the range of addresses. A plurality of address registers coupled to the plurality of the memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections. One of the plurality of the address registers specifies that a zero portion of the range of the addresses is assigned to one of the plurality of memory sections if the at least one of the plurality of the memory sections is defective.

Claims

1. A memory device addressable over a range of addresses, the memory device comprising:

plurality of independently addressable memory sections, wherein each of the memory sections is assigned a portion of the range of addresses, each of the memory sections comprising an array of memory cells connected in rows and columns; and

a plurality of address registers coupled to the plurality of memory sections, each address register for storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections, and wherein at least one of the plurality of address registers specifies that a zero portion of the range of addresses is assigned to at least one of the plurality of memory sections if the at least one of the plurality of memory sections is defective.

2. The memory device of claim 1, wherein at least two of the plurality of memory sections correspond to contiguous portions of the range of addresses.

3. The memory device of claim 1, further comprising a plurality of sense amps, each sense amp being coupled to a column of the array of memory cells, each sense amp for sensing data stored in a selected memory cell, wherein a first subset of sense amps coupled to columns of a first memory section are for latching data sensed in the selected memory cells, and for transferring data that has been latched, wherein the columns of the first memory section are precharged to a value intermediate to logical 0 and 1 immediately after the data has been transferred such that the array of memory cells for the first memory section may be immediately sensed in response to a memory access request received after the data has been transferred.

4. The memory device of claim 3, wherein the first subset of sense amps latches data sensed in a previous memory access operation of the first memory section, the data latched by the first subset of sense amps being immediately available for access by subsequent memory operations of the first memory section.

5. The memory device of claim 4, wherein a second subset of sense amps coupled to columns of a second memory section latches data in a previous memory access operation of the second memory section, the data latched by the second plurality of sense amps being immediately available for access by subsequent memory operations of the second memory section.

6. The memory device of claim 3, wherein the memory device is formed on a single semiconductor substrate.

7. The memory device of claim 1, wherein the memory device is a dynamic random access memory device (DRAM).

8. A memory system addressable over a range of address, the memory system comprising:

a first memory device;

a second memory device;

wherein the first and second memory devices each comprise;

a plurality of independently addressable memory sections, wherein each of the memory sections corresponds to a portion of the range of addresses; and

a plurality of address registers coupled to the plurality of memory sections, each address register storing information indicating a portion of the range of addresses that corresponds to one of the plurality of memory sections, wherein at least one of the plurality of address registers in the first or second memory device specifies that a zero portion of the range of addresses is assigned to at least one of the plurality of memory sections in the first or second memory device if the at least one of the plurality of memory sections is defective.

9. The memory system of claim 8, wherein a first address register in the first memory device stores first information and a second address register in a second device stores second information such that corresponding first and second memory sections respond to a contiguous range of addresses within the range of addresses.

10. The memory system of claim 8, wherein the first memory device is a dynamic random access memory device (DRAM).

11. The memory system of claim 10, wherein the second memory device is a dynamic random access memory device (DRAM).

12. The memory system of claim 8, wherein the first memory device is formed on a first single semiconductor substrate.

13. The memory system of claim 12, wherein the second memory device is formed on a second single semiconductor substrate.