Advanced integrated avionics testing system

• US 5,638,383 A
• Filed: 07/24/1992
• Issued: 06/10/1997
• Est. Priority Date: 07/24/1992
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Inc. (Northrop Grumman Corporation)
• Inventors: Wotzak, William J., Fecteau, Kenneth P.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): CHOI, KYLE JAEHUN
• Application Number:
  US07/920,340
• Time in Patent Office: 1,782 Days
• Field of Search: 364/550, 364/551.01, 364/580, 364/152, 364/158, 364/159, 364/160, 364/186, 364/179, 364/579, 371/22.5
• US Class Current: 714/733
• CPC Class Codes: B64G 1/22 Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
• CPC Class Codes: G05B 23/0256 injecting test signals and analyzing monitored process response, e.g. injecting the test signal while interrupting the normal operation of the monitored system; superimposing the test signal onto a control signal during normal operation of the monitored system
• CPC Class Codes: G05D 1/0055 with safety arrangements

Abstract

Apparatus, and a related method, for testing complex integrated systems, such as avionics systems. A unified approach to the testing architecture provides for a selection of on-line and off-line tests to be run on a complex system, at selected hierarchical levels. Built-in test logic is provided on each component or chip to be tested, and additional built-in test logic is provided at a module level, where a module includes multiple chips or components of various types. Module testing is, in turn, controlled in part by a maintenance processor responsible for multiple modules, and the maintenance processor is controlled in part by a maintenance executive. The testing architecture can be configured to provide a desired mix of performance testing, processor testing and physical testing of components.

Claims

1. A built-in testing architecture providing on-equipment fault detection and isolation capability, for complex integrated electronic systems having multiple components assembled onto at least one module, the built-in testing architecture comprising:

built-in component test means incorporated into multiple components of a complex electronic system, for performing physical tests on the components;

built-in module test means incorporated into each module of a complex electronic system, wherein each module includes multiple components, and wherein the built-in module test means on a module coordinates operations of built-in component test means for components on the same module;

built-in maintenance processor means, for coordinating testing operations of multiple built-in module test means; and

built-in maintenance executive test means, for coordinating operations of the maintenance processor means.

2. A built-in testing architecture as defined in claim 1, wherein the built-in module test means includes:

means for injecting predefined test signals at selected points in the module;

means for controlling operation of the module at a controllable rate once the test signals have been injected; and

means for observing signal states at selected points in the module during its operation on the test signals.

3. A built-in testing architecture as defined in claim 1, wherein the built-in component test means includes:

a plurality of multiplexers coupled to inputs of flip-flops in a component; and

control means, for selecting between two sets of inputs to the multiplexers, wherein selection of a first set of inputs to the multiplexers configures the component to perform its normal and intended operations, and selection of a second set of inputs to the multiplexers configures the component such that the flip-flops are connected in a serial chain for the introduction or retrieval of test data;

and wherein the built-in module test means further includes means for storing a sequence of instructions for controlling the built-in component test means to perform a desired physical test sequence on at least one component.

4. A built-in testing architecture as defined in claim 3, wherein the maintenance processor means and the maintenance executive test means include means for initiating at least one functional test, in which a signal is injected into a selected point in a module or component and its effect is monitored at other selected points.

5. A built-in testing architecture as defined in claim 1, wherein the maintenance processor means and the maintenance executive test means include means for initiating at least one functional test, in which a signal is injected into a selected point in a module or component and its effect is monitored at other selected points.

6. A method of operation of a built-in testing architecture, for testing complex integrated electronic systems having multiple components assembled onto at least one module, the method comprising the steps of:

performing physical tests on multiple components with built-in component testing logic incorporated into components of a complex electronic system;

coordinating, in built-in module testing logic incorporated into a module, the operations of built-in component testing logic incorporated into components of the complex system;

coordinating, in a built-in maintenance processor, the testing operations of built-in module testing logic; and

coordinating, in a built-in maintenance executive test processor, overall operations of at least one maintenance processor.

7. A method as defined in claim 6, wherein the step of coordinating module testing includes:

injecting predefined test signals at selected points in the module;

controlling operation of the module at a controllable rate once the test signals have been injected; and

observing signal states at selected points in the module during its operation on the test signals.

8. A method as defined in claim 6, wherein the step of coordinating the operations of built-in component testing logic includes:

multiplexing operational signals and test signals in a plurality of multiplexers coupled to inputs of flip-flops in a component; and

selecting between two sets of inputs to the multiplexers, wherein selection of a first set of inputs to the multiplexers configures the component to perform its normal and intended operations, and selection of a second set of inputs to the multiplexers configures the component such that the flip-flops are connected in a serial chain for the introduction or retrieval of test data;

and wherein the step of coordinating operations of a module includes storing a sequence of instructions for controlling performance of a desired physical test sequence on at least one component.

9. A method as defined in claim 8, and further comprising the step of:

initiating at least one functional test, in which a signal is injected into a selected point in a module or component and its effect is monitored at other selected points.

10. A method as defined in claim 6, and further comprising the step of:

initiating at least one functional test, in which a signal is injected into a selected point in a module or component and its effect is monitored at other selected points.

11. For use in a built-in testing architecture for testing complex integrated electronic systems having multiple components assembled onto at least one module, a module maintenance node for coordinating testing at a module level, the module maintenance node comprising:

means integrated with the module, for switching operation of the module to a functional mode in which the module performs its normal functions;

means integrated with the module, for switching operation of the module to a test mode in which data signals are transmitted to and received from the module maintenance node;

built-in means for generating test signals for transmission to the module operating in the test mode;

means for receiving and analyzing test signals received from the module operating in the test mode; and

built-in processor means for controlling all the aforementioned means in the module maintenance node.