Fast data transfer bus

• US 5,638,402 A
• Filed: 09/27/1994
• Issued: 06/10/1997
• Est. Priority Date: 09/27/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Inoue, Masao, Ogura, Toshihiko, Osaka, Hideki
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US08/313,384
• Time in Patent Office: 987 Days
• Field of Search: 375/257, 375/219, 375/220, 375/316, 333/32
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver. The bus receiver in the first bus transceiver generates a pulse signal substantially equal to an output pulse signal which was generated from the bus driver in the second bus transceiver, based on a pulse waveform induced in the parallel coupling portion on the first bus connecting line by the output pulse signal from the second bus transceiver.

Claims

1. A fast data transfer bus, comprising:

first and second bus connecting lines each for transferring a data pulse signal;

a first bus transceiver connected to one end of said first bus connecting line;

a first termination resistor connected to the other end of said first bus connecting line for impedance matching;

a second bus transceiver connected to one end of said second bus connected line;

a second termination resistor connected to the other end of said second bus connecting line for impedance matching; and

a supporting member for holding substantially constant an interval between said first and second bus connecting lines over a parallel coupling portion of a predetermined length of said first and second bus connecting lines for producing capacitive and inductive coupling between both of said bus connecting lines, said supporting member having a ground layer provided on one side of said first and second bus connecting lines so as to be spaced therefrom through an insulating material,

wherein each of said first and second bus transceivers includes a bus driver and a bus receiver, and

wherein further a bus receiver in one of said bus transceivers generates a pulse signal substantially equal to an output pulse signal which was generated by a bus driver in the other of said bus transceivers, based on forward crosstalk induced by said output pulse signal at said parallel coupling portion on a bus connecting line which is connected to said one bus transceiver, and

at said parallel coupling portion on said first and second bus connecting lines, a direction from said first bus transceiver to said first termination resistor is reverse to a direction from said second bus transceiver to said second termination resistor.

2. A bus according to claim 1, wherein said bus receiver includes an analog integrating circuit for generating a single pulse signal substantially equal to said output pulse in response to two sequential pulse waveforms of opposite polarities induced in said parallel coupling portion on a bus connecting line which is directly connected to an associated bus transceiver.

3. A bus according to claim 1, wherein said bus receiver includes:

a first comparator for directly receiving a first one of two sequential pulse waveforms of opposite polarities induced in said parallel coupling portion on the bus connecting line, which is directly connected to the associated bus transceiver, to compare said first one voltage to output a pulse;

a second comparator for directly receiving a second pulse waveform of said two sequential pulse waveforms, to compare said second pulse waveform with a second reference voltage to output a pulse; and

a frequency divider for receiving said pulses from said first and second comparators and generating a single pulse signal substantially equal to said output pulse.

5. A bus according to claim 1, wherein said first and second termination resistors are connected to a ground potential.

6. A bus according to claim 1, wherein said first and second termination resistors are connected to a potential equal to or less than a power supply voltage applied to said first and second bus transceivers.

7. A bus according to claim 6, wherein said bus driver includes an open drain type MOS transistor having its drain terminal connected to a bus connecting line which is directly connected to an associated bus transceiver.

8. A bus according to claim 6, wherein said bus driver includes a open collector type bipolar transistor having its collector terminal connected to a bus connecting line which is directly connected to an associated bus transceiver.

9. A bus according to claim 1, further comprising connector means arranged between said second bus transceiver and said parallel coupling portion, such that said second bus transceiver is rendered removable from and mountable on said second bus connecting line by said connector means even when said second bus is operating.

10. A bus according to claim 1, wherein said first and second bus connecting line portions in said parallel coupling portion are arranged on different layers of a multi-layer board, one surface of which is grounded, with their vertical positions being aligned, and each of said bus connecting line portions is surrounded horizontally by lines connected to the ground potential.

11. A bus according to claim 1, further comprising connector means between said printed circuit board and the rest of said first and second bus connecting line portions, such that said parallel coupling portion on said printed circuit board is rendered removable from and mountable on said rest of the bus connecting line portions.

12. A bus according to claim 11, further comprising connector means arranged between said first bus transceiver and said parallel coupling portion and connector means arranged between said second bus transceiver and said parallel coupling portion, such that said first bus transceiver and said second bus transceiver are rendered removable from and mountable on the rest of the bus connecting line portions.

13. A bus according to claim 1, wherein said first and second bus transceivers are included in first and second signal processing means, respectively.

14. A bus according to claim 1, wherein said first and second bus transceivers are provided as discrete parts from first and second signal processing means connected directly thereto through respective signal lines.

16. A bus according to claim 1, further comprising voltage dividing resistors for producing two reference voltages from a power supply voltage, and wherein:

said bus driver in said other bus transceiver is constituted by an open-drain type transistor, an open-collector type transistor or push-pull type transistors,

the other end of one bus connecting line associated with the other bus transceiver is terminated to a potential substantially half of said power supply voltage via an associated termination resistor,

the other end of the other bus connecting line associated with said one bus transceiver is terminated to said potential via an associated termination resistor,

one end of said the other bus connecting line is connected to said bus receiver in said one bus transceiver, and

said two reference voltages are applied to said bus receiver.

4. A fast data transfer bus comprising:

first and second bus connecting lines each for transferring a data pulse signal;

a first bus transceiver connected to one end of said first bus connecting line;

a first termination resistor connected to the other end of said first bus connecting line for impedance matching;

a second bus transceiver connected to one end of said second bus connecting line;

a second termination resistor connected to the other end of said second bus connected line for impedance matching; and

a supporting member for holding substantially constant an interval between said first and second bus connecting lines over a parallel coupling portion having a predetermined length of said first and second bus connecting lines for producing capacitive and inductive coupling between both of said bus connecting lines,

wherein each of said first and second bus transceivers includes a bus driver and a bus receiver, and the bus receiver in one of said bus transceivers generates a pulse signal substantially equal to an output pulse signal which was generated by a bus driver in the other of said bus transceivers, based on a pulse waveform induced by said output pulse signal in said parallel coupling portion on the bus connecting line which is connected to said one bus transceiver,

wherein said bus receiver includes;

a first comparator for comparing a first pulse waveform of two sequential pulse waveforms of opposite polarities induced in said parallel coupling portion on a bus connecting line, which is directly connected to an associated bus transceiver, with a first reference voltage to output a pulse,

a second comparator for comparing a second pulse waveform of said two sequential pulse waveforms with a second reference voltage to output a pulse,

a first frequency divider connected to said first comparator,

a second frequency divider connected to said second comparator, and

logic means for taking exclusive OR of outputs from said first and second frequency dividers to generate a single pulse signal substantially equal to said output pulse.

15. A fast data transfer bus comprising:

a first bus connecting line for transferring a data pulse signal;

a first bus transceiver connected to one end of said first bus connecting line;

a first termination resistor connected to the other end of said first bus connecting line for impedance matching;

a second bus transceiver connected to the other end of said first bus connecting line;

a second termination resistor connected to the one end of said first bus connecting line;

a second bus connecting line for transferring a data pulse signal;

a third bus transceiver connected to one end of said second bus connecting line;

a third termination resistor connected to the other end of said second bus connecting line for impedance matching;

a fourth bus transceiver connected to the other end of said second bus connecting line;

a fourth termination resistor connected to the one end of said second bus connecting line for impedance matching; and

a supporting member for holding substantially constant an interval between said first and second bus connecting lines in a parallel coupling portion of a predetermined length of said first and second bus connecting lines for producing capacitive and inductive coupling between both said bus connecting lines, said supporting member having around layer provided on one side of said first and second bus connecting lines so as to be spaced therefrom through an insulating material,

wherein each of said first, second, third, and fourth bus transceivers includes a bus driver and a bus receiver, and the bus receiver in each of the bus transceivers connected to one bus connecting line generates a pulse signal substantially equal to an output pulse signal which was generated by the bus driver in each of the bus transceivers connected to the other bus connecting line, based on forward and backward crosstalk induced by said output pulse signal in said parallel coupling portion on said one bus connecting line, and

direct data transfer is enabled between said first and second transceivers and between said third and fourth transceivers.