Method and system for aligning the phase of high speed clocks in telecommunications systems

• US 5,638,410 A
• Filed: 10/14/1993
• Issued: 06/10/1997
• Est. Priority Date: 10/14/1993
• Status: Expired due to Fees

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Inventors: Kuddes, David W.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/136,339
• Time in Patent Office: 1,335 Days
• Field of Search: 375/118, 375/119, 375/120, 375/357, 375/371, 375/373, 375/374-376, 370/102, 370/108, 307/510, 307/511, 307/514, 328/133, 331/17, 331/25, 327/12, 327/3, 327/24, 327/5, 327/7, 327/149, 327/156, 327/161, 327/163
• US Class Current: 375/357
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360°, between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Claims

1. A method for negating a phase difference between clock signals in a high-speed telecommunications system, comprising the steps of:

detecting the phase difference between a first clock signal and at least a second clock signal, linearly over a range between and including 0 and 360 degrees;

calculating the time required to delay the second clock signal by an amount required to negate said phase difference; and

shifting the phase of said second clock signal in correspondence with the calculated amount.

2. A system for negating a phase difference between a plurality of clock signals in a high-speed telecommunications system, comprising:

a first circuit operable to detect a phase difference linearly, over a range between and including 0 and 360 degrees, between a first clock signal and at least a second clock signal;

a second circuit coupled to said first circuit and operable to generate an error signal at an output corresponding to said phase difference; and

a third circuit coupled to said output of said second circuit and operable to shift the phase of said second clock signal and thereby minimize said error signal.

3. The system of claim 2, wherein said first circuit comprises an XOR phase detection circuit.

4. The system of claim 2, wherein said third circuit comprises a digital delay line.

5. A method for aligning the phase of a plurality of high-speed frequency-synchronous clock signals, comprising the steps of:

detecting the phase of a first high-speed clock signal and the phase of at least a second high-speed clock signal;

generating an error signal corresponding to a difference between the phase of said first clock signal and the phase of said second clock signal, linearly over a range between and including 0 and 360 degrees;

calculating the time required to shift the phase of said second clock signal by an amount required to cancel the error signal; and

delaying said second clock signal by the required amount.

6. A system for aligning the phase of a plurality of high-speed frequency-synchronous clock signals, comprising:

clock generator circuitry operable to generate a first high-speed clock signal;

phase detector circuitry operable to detect a phase difference between said first clock signal and at least a second high-speed clock signal, linearly over a range between and including 0 and 360 degrees;

error signal generating circuitry connected to said phase detector circuitry and operable to generate an error signal corresponding to said phase difference between said first high-speed clock signal and said at least second high-speed clock signal;

processing circuitry operable to receive said error signal and calculate the time required to shift the phase of said first high-speed clock signal by an amount required to cancel the error signal; and

time delay circuitry operable to shift the phase of said first high-speed clock signal responsive to said calculated amount.

7. The system of claim 6, wherein said clock generator circuitry comprises a phase-locked loop circuit.

8. The system of claim 6, wherein said phase detector circuitry comprises an XOR phase detector circuit.

9. The system of claim 6, wherein said processing circuitry comprises a microprocessor.

10. The system of claim 6, wherein said time delay circuitry comprises a digital delay line.