Trenched DMOS transistor fabrication having thick termination region oxide

• US 5,639,676 A
• Filed: 02/16/1996
• Issued: 06/17/1997
• Est. Priority Date: 08/15/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/603,047
• Time in Patent Office: 487 Days
• Field of Search: 437/40 DM, 437/40 RG, 437/41 DM, 437/41 RG, 437/203, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/490, 257/491, 257/495
• US Class Current: 438/270
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Claims

1. A method for forming a field effect transistor comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

forming a patterned mask layer on the principal surface;

forming a doped deep body region of a second conductivity type of the transistor in a portion of the substrate underlying the portions of the principal surface exposed by the patterned mask layer;

locally growing oxide on the principal surface at those portions of the principal surface exposed by the patterned mask layer including on a portion of a termination region of the transistor and extending to an outer edge of the termination region beyond an outer edge of an underlying doped region;

removing the patterned mask layer, thereby exposing additional portions of the principal surface; and

forming in those portions of the substrate underlying the exposed additional portions of the principal surface a doped body region, a doped source region, and a gate region of the transistor.

2. A method for forming a field effect transistor comprising:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

forming a patterned mask layer on the principal surface;

doping semiconductor regions of a second conductivity type in portions of the substrate exposed by the mask layer, thereby forming deep body regions of the transistor;

growing an oxide layer on portions of the principal surface exposed by the mask layer including on a portion of a termination region of the transistor and extending to an outer edge of the termination region beyond an outer edge of an underlying doped region;

forming a plurality of trenches in the substrate;

forming a conductive material layer in the trenches and over at least a part of the oxide layer, the portion of the conductive material layer in the trenches being a gate of the transistor;

forming doped first regions of the second conductivity type in the substrate extending from the portions of the substrate exposed by the mask layer at the principal surface into the substrate;

forming doped second regions of the first conductivity type extending from the portions of the substrate exposed by the mask layer at the principal surface into the substrate, the first and second doped regions respectively being body and source regions of the transistor;

forming a patterned insulating layer overlying the principal surface and the conductive material layer; and

forming a patterned interconnect layer overlying the principal surface and over the patterned insulating layer and contacting the deep body, body, and source regions, and the gate.

3. The method of claim 2, wherein the oxide layer is at least 5000 Å

thick.

4. The method of claim 2, wherein the step of forming a conductive material layer comprises forming a portion of the conductive material layer in the termination region of the transistor;

and further comprising the step of;

electrically connecting the portion of the conductive material layer in the termination region to the underlying doped region.

5. The method of claim 4, wherein the conductive material layer is a field plate, and wherein the at least one doped semiconductor region in the termination region is a guard ring, and further comprising the step of forming a guard ring conductive contact overlying and in contact with the guard ring and also contacting the field plate.

6. The method of claim 5, wherein the oxide layer extends from the outer edge of the termination region laterally inward to the guard ring conductive contact.