Double dense ferroelectric capacitor cell memory

• US 5,640,030 A
• Filed: 05/05/1995
• Issued: 06/17/1997
• Est. Priority Date: 05/05/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kenney, Donald McAlpine
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/435,679
• Time in Patent Office: 774 Days
• Field of Search: 365/145, 257/295, 257/296, 257/298, 257/312, 257/532, 257/595
• US Class Current: 257/296
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements

Abstract

A semiconductor memory is provided wherein two bits of binary information are stored simultaneously in a ferroelectric capacitor by utilizing the positive and negative polarization states of the ferroelectric capacitor for storing a first of the two bits of binary information and by utilizing the capacitive characteristic of the ferroelectric capacitor to simultaneously store a second of the two bits of binary information without altering the polarization of the ferroelectric capacitor. When reading information from the ferroelectric capacitor, the second of the two bits of information is read out first and transferred to a buffer cell, then the first of the two bits of binary information is read and re-written, as desired, and the second of the two bits of information is returned from the buffer cell to the ferroelectric capacitor.

Claims

1. A semiconductor memory comprising

a ferroelectric capacitor having first and second polarization states and a volatile storage mechanism, and

voltage means for applying a first voltage having a given magnitude to said ferroelectric capacitor to select one of said first and second polarization states to store a 0 or 1 binary digit, respectively, in said ferroelectric capacitor and for subsequently applying a second voltage having a magnitude significantly smaller than said given magnitude to said ferroelectric capacitor to simultaneously store a 0 or 1 binary digit in the volatile storage mechanism of said ferroelectric capacitor.

2. A semiconductor memory as set forth in claim 1 further including a bit line, a plate line and a transfer switch connected serially with said ferroelectric capacitor and disposed between said bit line and said plate line, said means applying said first and second voltages between said bit line and said plate line.

3. A semiconductor memory as set forth in claim 2 wherein said transfer switch is a field effect transistor having a gate electrode and further including a word line connected to the gate electrode and given means for applying a voltage to said word line to turn on said transistor while said first and second voltages are being applied to said bit line and plate line.

4. A semiconductor memory as set forth in claim 1 wherein said voltage means includes a power supply source having a voltage of said given magnitude for providing said first voltage and said second voltage has a magnitude of a small fraction of said given magnitude.

5. A semiconductor memory as set forth in claim 4 wherein said given voltage magnitude is approximately 5 volts and the magnitude of said second voltage is approximately 1 volt.

6. A semiconductor memory as set forth in claim 3 wherein said voltage means applies the first voltage to either said bit line or to said plate line depending upon the 0 or 1 binary digit to be stored in one of the polarization states of said ferroelectric capacitor and a 0 voltage on the other of said lines and applies to said plate line a voltage having a magnitude approximately one half that of the given magnitude to store a 0 or 1 binary digit in the volatile storage mechanism of said ferroelectric capacitor.

7. A semiconductor memory as set forth in claim 6 wherein the magnitude of the first voltage is 5 volts.

8. A semiconductor memory comprising

means including a ferroelectric capacitor having a non-volatile mechanism storing first data therein and a volatile storing mechanism simultaneously storing second data therein,

a bit line,

a plate line,

a transfer switch connected serially with said ferroelectric capacitor between said bit line and said plate line,

reference voltage means,

sensing means having first and second nodes, said bit line line and said reference voltage means being connected to the first and second nodes, respectively, of said sensing means,

a buffer cell connected to said bit line, and

means including word line and plate line decoder and driver means coupled to said transfer switch and to said plate line for reading the second data from said ferroelectric capacitor and for storing said second data into said buffer cell and for subsequently reading said second data from said buffer cell and for restoring said second data back into said ferroelectric capacitor without destroying the first data.

9. A semiconductor memory as set forth in claim 8 wherein said transfer switch is a field effect transistor having a gate electrode connected to said word line and plate line decoder and driver means and said buffer cell is a dynamic one device cell.

10. A semiconductor memory comprising

a ferroelectric capacitor including a non-volatile mechanism having first and second states and a volatile storing mechanism,

means for applying a first voltage to said ferroelectric capacitor to set said ferroelectric capacitor in one of said first and second non-volatile states to store a first binary digit of information in said ferroelectric capacitor and for subsequently applying a second voltage having a significantly smaller magnitude than that of said first voltage insufficient to erase the first binary digit to said ferroelectric capacitor to simultaneously store a second binary digit of information in the volatile storing mechanism of said ferroelectric capacitor,

a buffer cell,

means for reading the second binary digit of information stored in said ferroelectric capacitor and for transferring the second binary digit of information to said buffer cell, and means for reading the first binary digit of information stored in said ferroelectric capacitor.

11. A semiconductor memory as set forth in claim 10 wherein said non-volatile mechanism having first and second states includes positive and negative, respectively, polarization of said ferroelectric capacitor and said volatile storing mechanism includes capacitive characteristics of said ferroelectric capacitor.

12. A method of operating a ferroelectric capacitor cell memory for simultaneously storing first and second binary digits of information therein, said memory including a ferroelectric capacitor having a non-volatile mechanism having first and second states and a volatile storing mechanism and a buffer cell, the steps of the method comprising

applying a first voltage to said ferroelectric capacitor to set said ferroelectric capacitor in one of said first and second non-volatile states to store the first binary digit of information in said ferroelectric capacitor,

applying a second voltage having a smaller magnitude than that of the first voltage insufficient to erase the first binary digit to said ferroelectric capacitor after storing said first binary digit to simultaneously store a second binary digit of information in the volatile storing mechanism of said ferroelectric capacitor,

reading the second binary digit of information stored in said ferroelectric capacitor and transferring the second binary digit of information to said buffer cell, and

reading the first binary digit of information stored in said ferroelectric capacitor after storing the second binary digit of information in said buffer cell.

13. A method of operating a ferroelectric capacitor cell memory for simultaneously storing first and second binary digits of information therein, said memory including a ferroelectric capacitor having first and second polarization states and a volatile storage mechanism and a buffer cell, the steps of the method comprising

applying a first voltage to said ferroelectric capacitor to set the ferroelectric capacitor in one of the first and second polarization states to store the first binary digit of information in said ferroelectric capacitor,

applying a second voltage having a significantly smaller magnitude than that of the first voltage insufficient to erase the first binary digit to said ferroelectric capacitor after storing the first binary digit to simultaneously store the second binary digit of information in the volatile storage mechanism of said ferroelectric capacitor,

reading the second binary digit of information stored in said ferroelectric capacitor and transferring the second binary digit of information to said buffer cell, and

reading the first binary digit of information stored in the ferroelectric capacitor after storing the second binary digit in said buffer cell.

14. A method of operating a ferroelectric capacitor cell memory as set forth in claim 13, said first voltage applying step applying +5 or -5 volts across said ferroelectric capacitor to store the first binary digit of information in said ferroelectric capacitor and said second voltage applying step applying a +1 or -1 volt across said ferroelectric capacitor to simultaneously store the second binary digit of information in said ferroelectric capacitor.

15. A method of writing data into a ferroelectric capacitor having polarization states and a volatile storing mechanism and having a cell plate and a cell node that stores first logic states by altering polarization of the polarization states of said ferroelectric capacitor and that stores second logic states in the volatile storing mechanism that do not alter polarization of the polarization states of the ferroelectric capacitor, the steps of the method comprising

writing one of the first logic states in the ferroelectric capacitor with a first voltage,

setting the cell plate of the ferroelectric capacitor to 1/2 of the first voltage after the one of the first logic states is written in said ferroelectric capacitor, and

applying to the cell node of said ferroelectric capacitor a voltage equal to 1/2 of the first voltage + or - X volts, where X volts is insufficient to disturb the one of the first logic states, for writing one of the second logic states in the volatile storing mechanism of the ferroelectric capacitor.

16. A method of writing data to a ferroelectric capacitor as set forth in claim 15, wherein said writing with a first voltage is with 5 volts and said applying a voltage equal to 1/2 of the first voltage + or - X volts is with X equal to 1 volt.

17. A method of reading binary digit information from a ferroelectric capacitor that store non-volatile logic states that change the polarization of said ferroelectric capacitor and simultaneously stores volatile logic states that do not change the polarization of said ferroelectric capacitor, the steps of the method comprising

reading a stored volatile logic state from said ferroelectric capacitor and transferring it to a buffer cell,

after transferring the stored volatile logic state to the buffer cell, reading/writing the non-volatile logic state stored in the ferroelectric capacitor, and

re-writing the stored volatile logic state by transferring it from the buffer cell to the ferroelectric capacitor.

18. A semiconductor memory comprising

means including a multi-level data storage device having a non-volatile mechanism with first and second states for storing a first binary digit of information and a volatile storing mechanism for simultaneously storing a second binary digit of information,

a buffer cell,

a bit line connected to said multi-level data storage device and to said buffer cell,

sensing means connected to said bit line, and

means coupled to said sensing means, said multi-level data storage device and said buffer cell for transferring said second binary digit of information from said multi-level data storage device to said buffer cell through said bit line without destroying the first binary digit of information remaining in said multi-level data storage device.

19. A semiconductor memory as set forth in claim 18 wherein said buffer cell is a one device memory cell including a storage capacitor and a transfer switch disposed between said capacitor and said bit line.

20. A semiconductor memory as set forth in claim 18 wherein said multi-level data storage device is a ferroelectric cell having a ferroelectric capacitor and a transfer switch disposed between said ferroelectric capacitor and said bit line.