Top-drain trench based resurf DMOS transistor structure

• US 5,640,034 A
• Filed: 05/18/1992
• Issued: 06/17/1997
• Est. Priority Date: 05/18/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US07/883,985
• Time in Patent Office: 1,856 Days
• Field of Search: 257/335, 257/327, 257/330, 257/288, 257/329, 257/351, 257/341, 257/333, 257/343, 257/344
• US Class Current: 257/341
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

Claims

1. A high voltage power transistor, comprising:

a source formed at a top surface of the transistor;

a drain formed at the top surface of the transistor;

a gate formed in a trench between the source and drain; and

a nonuniform dielectric lining in the trench having a thin portion adjacent the source and a thick portion adjacent the drain.

2. The high voltage power transistor of claim 1 wherein the nonuniform dielectric lining is oxide.

3. A high voltage power transistor, comprising:

a substrate;

a drift region formed in a top face of the substrate;

a drain region formed in the drift region;

a p-well region formed in the top face of the substrate;

a source region formed in the p-well region;

a trench formed in the top face of the substrate between the drift region and the p-well region such that the trench makes contact with both the drift region and the p-well region;

a nonuniform dielectric lining in the trench having a thin portion adjacent the p-well region and a thick portion adjacent the drift region; and

a gate formed within the trench.

4. The high voltage power MOS transistor of claim 3 further comprising an isolation region formed in the face of the substrate below the p-well region to electrically isolate the source region from the substrate.

5. The high voltage power MOS transistor of claim 4 wherein the substrate and p-well region are P type semiconductor material and the source region, drain region, drift region, and isolation region are N type semiconductor material.

6. The high voltage power MOS transistor of claim 3 wherein the gate comprises:

a nonuniform dielectric lining within the trench, wherein the nonuniform dielectric lining includes a thin portion in the trench adjacent the source region and a thick portion in the trench adjacent the drain region; and

a conductive material overlying the nonuniform dielectric and substantially filling the trench.

7. The high voltage power MOS transistor of claim 6 wherein the nonuniform dielectric comprises:

a thin oxide lining on the trench wall adjacent the source; and

a thick oxide lining on the trench wall adjacent the drift region.