IC fault analysis system having charged particle beam tester

• US 5,640,098 A
• Filed: 01/30/1996
• Issued: 06/17/1997
• Est. Priority Date: 11/09/1993
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Kawamoto, Hiroshi, Kurihara, Masayuki, Iwai, Toshimichi, Niijima, Hironobu, Goishi, Akira
• Primary Examiner(s): Wieder, Kenenth A.
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/593,549
• Time in Patent Office: 504 Days
• Field of Search: 324/158.1, 324/751, 250/310, 250/311, 364/488
• US Class Current: 324/754.22
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: G01R 31/31912 Tester/user interface

Abstract

An IC fault analysis system which is capable of accurately correlating mask layout data and/or net listing data associated with CAD (computer aided design) data developed in the IC design and an image obtained by a non-contact type tester such as an electron beam tester. The IC fault analysis system includes a circuit diagram display for showing a circuit diagram of the IC device under test based on the CAD data, a mask layout display for showing a mask layout of the IC device under test based on the CAD data, a contrast image display for showing a potential distribution of the IC device under test obtained in the non-contact type tester, an input means connected to the circuit diagram display for specifying a circuit component of the IC device under test, a comparison means for comparing the circuit diagram of the circuit component defined by the input means and contrast image corresponding to the circuit component, and a comparison data memory for storing the comparison data of the comparison means and providing the comparison data to the contrast image display.

Claims

1. An IC fault analysis system for evaluating a semiconductor IC device, comprising:

a circuit diagram display for showing a circuit diagram of the IC device under test based on CAD (computer aided design) data;

a mask layout display for showing a mask layout of the IC device under test based on the CAD data;

a contrast image display for showing electric potential in each circuit component of the IC device under test obtained by a charged particle beam tester;

an input means connected to the IC fault analysis system for specifying a circuit component of the IC device under test;

a comparison means for comparing data associated with positions between the circuit diagram of the circuit component in the IC device specified by the input means and the contrast image corresponding to said circuit component; and

a comparison data memory for storing the comparison data from the comparison means and providing the comparison data to the contrast image display and the mask layout display;

wherein the specified circuit component in the IC device is highlighted on both the contrast image display and the mask layout display based on the data from the comparison data memory to correct positional errors caused by the CAD data and the charged particle beam tester.

2. An IC fault analysis system as defined in claim 1 further including:

a net listing display for showing a net list of each component in the IC device based on the CAD data, a specified part of the net list being highlighted for showing relationship with the corresponding component in the contrast image.

3. An IC fault analysis system as defined in claim 1 further including:

a waveform image display for showing a waveform of the component in the IC device defined by the input means, the waveform being obtained by the non-contact tester, a specified part of the waveform being highlighted for showing relationship with the corresponding component in the mask layout.

4. An IC fault analysis system for evaluating a semiconductor IC device, comprising:

a mask layout display for showing a mask layout of the IC device under test based on the CAD (computer aided design) data produced in a design stage of the semiconductor IC device;

a contrast image display for showing a potential distribution for circuit components in the IC device under test obtained by a charged particle beam tester including an electron beam tester;

an input means selectively connected to either the mask layout display or the contrast image display for specifying a portion of the circuit component in the IC device under test;

a comparison means for comparing data related to positions of the specified circuit component in the mask layout and the contrast image of the IC device specified by the input means; and

a comparison data memory for storing the comparison data of the comparison means and providing the comparison data to the mask layout display and the contrast image display;

wherein the specified circuit component in the IC device is highlighted on both the contrast image display and the mask layout display based on the data from the comparison data memory to correct positional errors caused by the CAD data and the charged particle beam tester.

5. An IC fault analysis system as defined in claim 4 further including:

a switch circuit for selectively connecting the input means to either of the mask layout display or the contrast image display to specify the circuit component in the IC device under test.

6. An IC fault analysis system as defined in claim 4 further including:

a net listing display for showing a net list of each component in the IC device based on the CAD data;

a waveform image display for showing a waveform of the circuit component in the IC device defined by the input means, the waveform being obtained by the non-contact tester;

a circuit diagram display for showing a circuit diagram of the IC device under test based on CAD data;

wherein images on the displays are correlated with respect the specified circuit component based on the data from the comparison data memory to establish positional relationship for the circuit component among the images.