Magnetic memory array using magnetic tunnel junction devices in the memory cells

• US 5,640,343 A
• Filed: 03/18/1996
• Issued: 06/17/1997
• Est. Priority Date: 03/18/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Parkin, Stuart Stephen Papworth, Kaufman, James Harvey, Gallagher, William Joseph, Scheuerlein, Roy Edwin
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/618,004
• Time in Patent Office: 456 Days
• Field of Search: 365/1, 365/2, 365/6, 365/16, 365/232, 365/55, 365/170, 365/171, 365/173, 365/158
• US Class Current: 365/171
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements

Abstract

A nonvolatile magnetic random access memory (MRAM) is an array of individual magnetic memory cells. Each memory cell is a magnetic tunnel junction (MTJ) element and a diode electrically connected in series. Each MTJ is formed of a pinned ferromagnetic layer whose magnetization direction is prevented from rotating, a free ferromagnetic layer whose magnetization direction is free to rotate between states of parallel and antiparallel to the fixed magnetization of the pinned ferromagnetic layer, and an insulating tunnel barrier between and in contact with the two ferromagnetic layers. Each memory cell has a high resistance that is achieved in a very small surface area by controlling the thickness, and thus the electrical barrier height, of the tunnel barrier layer. The memory cells in the array are controlled by only two lines, and the write currents to change the magnetic state of an MTJ, by use of the write currents'"'"' inherent magnetic fields to rotate the magnetization of the free layer, do not pass through the tunnel barrier layer. All MTJ elements, diodes, and contacts are vertically arranged at the intersection regions of the two lines and between the two lines to minimize the total MRAM surface area. The power expended to read or sense the memory cell'"'"'s magnetic state is reduced by the high resistance of the MTJ and by directing the sensing current through a single memory cell.

Claims

1. A nonvolatile memory array comprising:

a substrate;

a first plurality of electrically conductive lines formed on the substrate;

a second plurality of electrically conductive lines formed on the substrate and overlapping the first plurality of lines at a plurality of intersection regions;

a plurality of memory cells formed on the substrate, each memory cell being located at an intersection region between one of the first plurality of lines and one of the second plurality of lines, each memory cell comprising a diode and a magnetic tunnel junction electrically connected in series with the diode.

2. The memory array according to claim 1 wherein each of the magnetic tunnel junctions comprises:

a pinned ferromagnetic layer and an antiferromagnetic layer adjacent to and in contact with the pinned ferromagnetic layer for pinning the magnetization of the pinned ferromagnetic layer in a preferred direction and substantially preventing its rotation in the presence of an applied magnetic field caused by electrical current flowing through the lines at the intersection region;

a free ferromagnetic layer whose magnetization is free to rotate in the presence of an applied magnetic field caused by electrical current flowing simultaneously through both of the lines at the intersection region; and

an insulating tunneling layer located between the pinned and free ferromagnetic layers.

3. The memory array according to claim 2 wherein the pinned ferromagnetic layer and the antiferromagnetic layer in each of the memory cells form part of the lines in the second plurality of lines.

4. The memory array according to claim 1 wherein each of the magnetic tunnel junctions comprises:

a first ferromagnetic layer;

a second ferromagnetic layer having a coercivity higher than the coercivity of the first ferromagnetic layer; and

an insulating tunneling layer located between the first and second ferromagnetic layers.

5. The memory array according to claim 4 wherein the second ferromagnetic layer in each of the memory cells forms part of the lines of the second plurality of lines.

6. The memory array according to claim 1 further comprising a layer of insulative material located between the first plurality of lines and the second plurality of lines at regions other than the intersection regions for spacing apart the first and second pluralities of lines, whereby each of the pluralities of lines is formed in a separate plane on the substrate.

7. The memory array according to claim 1 further comprising first write circuitry coupled to the first plurality of lines and second write circuitry coupled to the second plurality of lines, whereby during a write operation current passing through the lines at an intersection region generates a magnetic field acting on the magnetic tunnel junction at the intersecting region.

8. The memory array according to claim 7 wherein the first and second write circuitry apply a reverse bias voltage to the diode at the intersection region during a write operation, whereby no current passes through the magnetic tunnel junction when write current is passing through the lines at the intersection region.

9. The memory array according to claim 7 wherein the first write circuitry includes sense circuitry for detecting tunnel current through a magnetic tunnel junction in a direction perpendicular to the substrate when the voltage across the diode is greater than the diode threshold voltage.

10. A magnetic memory array comprising:

a substrate;

a first set of parallel electrically conductive lines formed on the substrate;

a second set of parallel electrically conductive lines formed on the substrate generally perpendicular to the first set of lines and overlapping the first set of lines, the second set of lines being spaced from the first set of lines in a direction generally perpendicular to the substrate surface to define a plurality of intersection regions;

a plurality of memory cells, each memory cell being located in an intersection region between the lines and comprising a diode and a magnetic tunnel junction electrically connected in series with the diode, each of the magnetic tunnel junctions comprising first and second ferromagnetic layers separated by an insulating tunnel barrier, one of the ferromagnetic layers having a magnetization direction that is generally fixed in a plane parallel to the substrate surface and the other of the ferromagnetic layers having a magnetization direction capable of orientation parallel or antiparallel to the magnetization direction of the first ferromagnetic layer;

electrical circuitry coupled to the first and second sets of lines for passing write current through the lines to generate magnetic fields in the vicinity of the second ferromagnetic layers in the magnetic tunnel junctions to reorient the magnetizations of the second ferromagnetic layers and thereby alter the electrical resistance across the magnetic tunnel junctions in a direction perpendicular to the substrate, the circuitry providing a reverse bias voltage to the diodes when current is passing through the lines, whereby no current flows through the magnetic tunnel junctions in a direction perpendicular to the substrate when write current is passing through the lines.

11. The magnetic memory array according to claim 10 wherein the electrical circuitry senses tunnel current through a magnetic tunnel junction in a direction perpendicular to the substrate when the voltage across the diode is greater than the diode threshold voltage.

12. The memory array according to claim 10 further comprising a layer of insulative material located between the first set of lines and the second set of lines at regions other than the intersection regions for spacing apart the first and second sets of lines, whereby each of the sets of lines is formed in a separate plane on the substrate.

13. A magnetic memory cell for use in a nonvolatile magnetic memory array that is connected to read/write circuitry for reading and writing to the memory cells in the array, the memory cell comprising:

a diode having a first electrical lead for connection to the read/write circuitry;

a fixed ferromagnetic layer electrically connected to the diode and having a magnetization in the plane of said fixed ferromagnetic layer that is fixed from rotation when exposed to a magnetic field less than a predetermined field strength;

an insulating tunnel barrier layer in contact with the fixed ferromagnetic layer;

a free ferromagnetic layer in contact with the tunnel barrier layer and having a magnetization free to rotate in the plane of said free ferromagnetic layer between directions parallel and antiparallel to the magnetization of the fixed ferromagnetic layer when exposed to a magnetic field less than said predetermined field strength, the free ferromagnetic having a second electrical lead for connection to the read/write circuitry; and

wherein the diode, the fixed ferromagnetic layer, the tunnel barrier layer and the free ferromagnetic layer are formed as a vertical stack oriented generally perpendicular to the plane of the ferromagnetic layers with the first electrical lead being at the bottom of the stack and the second electrical lead being at the top of the stack;

whereby during a write operation when write current from the read/write circuitry passes generally horizontally through the first and second electrical leads, the diode prevents current flow through the tunnel barrier layer and the magnetic field from the write current rotates the magnetization of the free ferromagnetic layer, and during a read operation when the voltage between the first and second electrical leads is greater than the diode threshold voltage, read current flows through the tunnel barrier layer in a direction generally perpendicular to said ferromagnetic layers, the electrical resistance to said read current flow being determined by the magnetization orientation of said free ferromagnetic layer.