Flash memory system
First Claim
1. A flash memory system coupled with a host computer comprising:
- a plurality of flash memory chips, anda flash memory controller for controlling transfer of data between said memory chips and said host computer,said flash memory controller comprisinga plurality of data buses each coupled with a related flash memory chip for transferring data to/from said flash memory chips,an address buffer coupled with said data buses through gates, to supply address information to said flash memory chips through said data buses,a plurality of buffer memories each coupled with a related data bus and said host computer for storing data to be transferred to/from a flash memory chip temporarily,a flash memory sequencer for controlling said data buses and said buffer memories simultaneously so that a plurality of flash memory chips are accessed simultaneously in parallel form,a plurality of comparators for comparing status information supplied by a related flash memory chip with predetermined reference information, andan AND circuit for providing logical AND operation for outputs of said comparators so that said AND circuit provides a positive output signal only when all the flash memory chips operate correctly in a previous operation.
1 Assignment
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Accused Products
Abstract
A flash memories (20, 21) are coupled with a host computer (1) through a flash memory controller (2) which has a pair of data buses (27, 28), and a pair of buffer memories (22, 23). Each of said data buses is coupled with a related flash memory, and a related buffer memory, which is coupled with said host computer. Said data buses (22, 23) are controlled to operate simultaneously so that said flash memories are accessed simultaneously in parallel form. A data in said host computer is transferred to said flash memories through said buffer memories and said data buses, and vice versa. All the elements (20, 21, 2) are mounted on a plastics card (100) called a flash memory card, which is coupled with a host computer through a connector. Because of use of a plurality of buses operating in parallel form, the transfer time of data between a host computer and a flash memory card is shortened.
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Citations
8 Claims
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1. A flash memory system coupled with a host computer comprising:
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a plurality of flash memory chips, and a flash memory controller for controlling transfer of data between said memory chips and said host computer, said flash memory controller comprising a plurality of data buses each coupled with a related flash memory chip for transferring data to/from said flash memory chips, an address buffer coupled with said data buses through gates, to supply address information to said flash memory chips through said data buses, a plurality of buffer memories each coupled with a related data bus and said host computer for storing data to be transferred to/from a flash memory chip temporarily, a flash memory sequencer for controlling said data buses and said buffer memories simultaneously so that a plurality of flash memory chips are accessed simultaneously in parallel form, a plurality of comparators for comparing status information supplied by a related flash memory chip with predetermined reference information, and an AND circuit for providing logical AND operation for outputs of said comparators so that said AND circuit provides a positive output signal only when all the flash memory chips operate correctly in a previous operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A flash memory controller for controlling transfer of data between flash memory chips which are coupled with said controller and a host computer, comprising:
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a plurality of data buses each coupled with a related flash memory chip for transferring data to/from said flash memory chips, a plurality of buffer memories each coupled with a related data bus and said host computer for storing data to be transferred to/from a flash memory chip temporarily, and a flash memory control for controlling said data buses and said buffer memories simultaneously so that a plurality of flash memory chips are accessed simultaneously, including a plurality of comparators for comparing status information supplied by a related flash memory chip with predetermined reference information, and an AND circuit for providing logical AND operation for outputs of said comparators so that said AND circuit provides a positive output signal only when all the flash memory chips operate correctly in a previous operation.
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Specification