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Flash memory system

  • US 5,640,349 A
  • Filed: 01/18/1996
  • Issued: 06/17/1997
  • Est. Priority Date: 08/31/1994
  • Status: Expired due to Term
First Claim
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1. A flash memory system coupled with a host computer comprising:

  • a plurality of flash memory chips, anda flash memory controller for controlling transfer of data between said memory chips and said host computer,said flash memory controller comprisinga plurality of data buses each coupled with a related flash memory chip for transferring data to/from said flash memory chips,an address buffer coupled with said data buses through gates, to supply address information to said flash memory chips through said data buses,a plurality of buffer memories each coupled with a related data bus and said host computer for storing data to be transferred to/from a flash memory chip temporarily,a flash memory sequencer for controlling said data buses and said buffer memories simultaneously so that a plurality of flash memory chips are accessed simultaneously in parallel form,a plurality of comparators for comparing status information supplied by a related flash memory chip with predetermined reference information, andan AND circuit for providing logical AND operation for outputs of said comparators so that said AND circuit provides a positive output signal only when all the flash memory chips operate correctly in a previous operation.

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