Self-enabling pulse trapping circuit

• US 5,640,364 A
• Filed: 12/06/1995
• Issued: 06/17/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd, Williams, Brett
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/568,358
• Time in Patent Office: 559 Days
• Field of Search: 365/230.08, 365/233.5, 365/238.5, 365/189.05, 365/206, 365/230.06
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.

Claims

1. An integrated memory device comprising:

a control signal input for receiving a control signal;

an address latch input for receiving an address latch signal;

a signal trapping circuit coupled to the control signal input and the address latch

input and adapted to latch a transition in the control signal; and

filter circuitry to filter noise received on the control signal input.

2. An integrated memory device comprising:

a control signal input for receiving a control signal;

an address latch input for receiving an address latch signal; and

a signal trapping circuit coupled to the control signal input and the address latch input and adapted to latch a transition in the control signal, wherein the signal trapping circuit comprises;

a low transition latch circuit to latch a high to low transition in the control signal when the address latch signal is activated; and

a high transition latch circuit to latch a low to high transition in the control signal when the address latch signal is activated.

3. The integrated memory device of claim 2 wherein the low transition latch circuit comprises:

a latch circuit connected to the control signal input; and

an enable circuit connected to the latch circuit to enable the latch circuit in response to an active transition of the address latch signal and the control signal.

4. The integrated memory device of claim 2 wherein the signal trapping circuit further comprises:

a pulse generator circuit coupled to the low transition latch circuit and the high transition latch circuit to generate a pulse in response to an output of the low transition latch circuit and the high transition latch circuit.

5. The integrated memory device of claim 2 wherein the high transition latch circuit comprises:

a latch circuit connected to the control signal input; and

a latch circuit connected to the control signal input; and

an enable circuit connected to the latch circuit to enable the latch circuit in response to an active transition of the address latch signal and the control signal.

6. The integrated circuit memory of claim 2 wherein the control signal input is a write enable input.

7. The integrated circuit memory of claim 2 wherein the integrated circuit memory is a burst access memory.

8. An integrated memory circuit comprising:

a write enable input for receiving a write enable signal;

an address latch input for receiving an address latch signal; and

a signal trapping circuit coupled to the write enable input and the address latch input and adapted to latch a transition in the write enable signal, the signal trapping circuit comprising,

a low transition latch circuit to latch a high to low transition in the write enable signal when the address latch input is activated,

a high transition latch circuit to latch a low to high transition in the write enable signal when the address latch input is activated, and

a pulse generator circuit coupled to the low transition latch circuit and the high transition latch circuit to generate a pulse in response to an output of the low transition latch circuit and the high transition latch circuit.

9. The integrated memory circuit of claim 8 wherein the low transition latch circuit comprises:

a latch circuit connected to the write enable input; and

an enable circuit connected to the latch circuit to enable the latch circuit in response to an active transition of the address latch signal and the write enable signal.

10. The integrated memory circuit of claim 9 wherein the latch circuit comprises a pair of cross-coupled NAND gates.

11. The integrated memory circuit of claim 8 wherein the high transition latch circuit comprises:

a latch circuit connected to the write enable input; and

an enable circuit connected to the latch circuit to enable the latch circuit in response to an active transition of the address latch signal and the write enable signal.

12. The integrated memory circuit of claim 11 wherein the latch circuit comprises a pair of cross-coupled NOR gates.

13. The integrated memory circuit of claim 8 wherein the signal trapping circuit includes filter circuitry to filter noise received on the write enable input.

14. A method of latching a control signal in a memory circuit having a control signal input and an address latch input, the method comprising the steps of:

receiving an address latch signal on the address latch input;

receiving a control signal on the control signal input;

enabling a first latch circuit on an active transition of the address latch signal if the control signal is in a first logic state, or enabling a second latch circuit on an active transition of the address latch signal if the control signal is in a second logic state; and

latching a transition of the control signal.

15. The method of claim 14 wherein the step of latching a transition of the control signal comprises the step of:

latching a high to low transition in the control signal using the first latch circuit.

16. The method of claim 14 wherein the step of latching a transition of the control signal comprises the step of:

latching a low to high transition in the control signal using the second latch circuit.

17. The method of claim 14 where in the control signal is a write enable signal.