State machine architecture for concurrent processing of multiplexed data streams
First Claim
1. Apparatus for concurrently processing a plurality of data streams time-division multiplexed into a single stream, each of said data streams containing a plurality of data words and having a characteristic state vector, said apparatus comprising:
- a. read-write memory means having a plurality of addressable memory locations for storing said state vectors;
b. a pipeline for;
i. during an initial clock cycle;
(1) receiving an input data word from one of said data streams;
(2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream;
(3) receiving said predefined memory location address of said input state vector;
ii. during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector;
iii. during a final clock cycle;
(1) transferring said output data word to an outgoing data stream;
(2) transferring said output state vector to said predefined memory location address in said memory means; and
,c. control means coupled to said memory means and to said pipeline for synchronizing operation thereof.
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Accused Products
Abstract
A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved. The process repeats sequentially, with the next group of three clock cycles commencing immediately after the initial clock cycle of the immediately preceding group of three clock cycles.
36 Citations
10 Claims
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1. Apparatus for concurrently processing a plurality of data streams time-division multiplexed into a single stream, each of said data streams containing a plurality of data words and having a characteristic state vector, said apparatus comprising:
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a. read-write memory means having a plurality of addressable memory locations for storing said state vectors; b. a pipeline for; i. during an initial clock cycle; (1) receiving an input data word from one of said data streams; (2) receiving, from a predefined memory location address in said memory means, an input state vector characterizing said one data stream; (3) receiving said predefined memory location address of said input state vector; ii. during one or more intermediate clock cycles, processing said input data word and said input state vector to yield an output data word and an output state vector; iii. during a final clock cycle; (1) transferring said output data word to an outgoing data stream; (2) transferring said output state vector to said predefined memory location address in said memory means; and
,c. control means coupled to said memory means and to said pipeline for synchronizing operation thereof. - View Dependent Claims (2, 3, 4, 5)
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6. A method of concurrently processing a plurality of data streams time-division multiplexed into a single stream, said method comprising the steps of:
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a. for each one of said data streams, storing a state vector characteristic of said one stream in a read-write memory location having a predefined address; b. during an initial clock cycle; i. receiving a next sequential data word from said single stream, said data word originating in one of said plurality of data streams; ii. retrieving from one of said memory locations an input state vector characteristic of said originating one of said plurality of data streams; c. after said initial clock cycle, delivering said data word and said input state vector to a state machine logic means and then, during one or more intermediate clock cycles following said initial clock cycle, processing said data word and said input state vector in said state machine logic means to produce an output data word and an output state vector; d. during a final clock cycle following said one or more intermediate clock cycles; i. transferring said output data word to an outgoing data stream; ii. storing said output state vector in said memory location from which said input state vector was retrieved; and
,e. sequentially repeating said steps b, c and d. - View Dependent Claims (7, 8, 9, 10)
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Specification