Single chip network router

• US 5,640,399 A
• Filed: 09/18/1995
• Issued: 06/17/1997
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Rostoker, Michael D., Stelliga, D. Tony
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): VU, HUY DUY
• Application Number:
  US08/529,656
• Time in Patent Office: 638 Days
• Field of Search: 370/85.13, 370/85.14, 370/85.1, 370/60, 370/60.1, 370/61, 370/58.1, 370/94.1, 370/110.1, 370/99, 370/105.1, 370/13, 370/17, 370/92, 370/351, 370/389, 370/392 , 370/393, 370/395, 370/396, 370/397, 370/398, 370/399, 370/400, 370/401, 370/402, 370/403, 370/404, 370/405, 370/410, 370/428, 370/429, 370/465, 370/466, 370/467 , 370/469, 370/470, 370/471, 370/472, 370/475, 370/476, 370/503, 370/509, 370/522, 370/252
• US Class Current: 370/392
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Claims

1. A single chip router for a multiplex communication network, comprising:

a packet memory for storing data packets;

a processor for processing said packets including converting said packets between a first protocol and a second protocol;

at first protocol interface unit;

a second protocol interface unit;

a memory controller for transferring packets in said first and second protocols between the processor and the memory, for transferring packets in said first protocol between the memory and the first protocol interface unit and for transferring packets in said second protocol between the memory and the second protocol interface unit; and

an address window filter for identifying a source or destination address of a packet being processed by examining only a predetermined portion of said address;

the address window filter including a dynamic window filter.

2. A single chip router for a multiplex communication network, comprising:

a packet memory for storing data packets;

a processor for processing said packets including converting said packets between a first protocol and a second protocol;

a first protocol interface unit;

a second protocol interface unit;

a memory controller for transferring packets in said first and second protocols between the processor and the memory, for transferring packets in said first protocol between the memory and the first protocol interface unit, and for transferring packets in said second protocol between the memory and the second protocol interface unit; and

an address window filter for identifying the address of a packet being converted by examining only a predetermined portion of said address;

in which

the address window filter comprises a dynamic window filter; and

the dynamic window filter comprises means for determining said predetermined portion of said address for examination by determining a common address range of addresses of packets processed by the router.

3. A router, comprising:

a processor for processing data packets;

a packet attribute memory for storing attributes of said data packets;

an attribute processor for performing a non-linear algorithm on a source or destination address of a packet being processed for accessing a corresponding attribute of said packet being processed in the packet attribute memory; and

an address window filter for identifying said address of said packet being processed by examining only a predetermined portion of said address;

the address window including a dynamic window filter.

4. A router, comprising:

a processor for processing data packets;

a packet attribute memory for storing attributes of said data packets;

an attribute processor for performing a non-linear algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet being processed in the packet attribute memory; and

an address window filter for identifying said address of said packet being processed by examining only a predetermined portion of said address;

in which

the address window filter comprises a dynamic window filter; and

the dynamic window filter comprises means for determining said predetermined portion of said address for examination by determining a common address range of addresses of packets processed by the router.