Digital downconverter/despreader for direct sequence spread spectrum communications system

• US 5,640,416 A
• Filed: 06/07/1995
• Issued: 06/17/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: COMSAT Corporation (Reorganized ISA SA)
• Original Assignee: COMSAT Corporation (Reorganized ISA SA)
• Inventors: Chalmers, Harvey
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): GLUCK, JEFFREY WILLIAM
• Application Number:
  US08/478,669
• Time in Patent Office: 741 Days
• Field of Search: 375/200, 375/206, 375/350, 375/371
• US Class Current: 375/147
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop

Abstract

A digital despreader and downconversion technique useful for spread spectrum communications receivers digitally tracks a timing phase of a PN sequence without the need for steering an external hardware clock. An additional benefit of the technique is the use of a receive filter matched to the bandlimited transmit chip sequence prior to despreading which reduces the amount of noise present after despreading. A narrowband filter also permits the use of a single A/D converter in the receiver, IF sampling at a relatively low sample rate compared to other techniques. A method for reducing a total number of computations required thereby facilitating implementation in a single custom digital integrated circuit is also described.

Claims

1. An apparatus for digitally downconverting and despreading an analog direct sequence spread spectrum signal, comprising:

a free-running, non-steered, clock generator which outputs an A/D sample clock;

the A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal;

an A/D converter which receives the spread spectrum signal and the A/D sample clock and outputs a digitized signal from the spread spectrum signal;

a local pseudo-noise sequence signal generator which outputs a local pseudo-noise sequence signal; and

a complex downconverter/polyphase filter which receives the digitized signal and the A/D sample clock and a sample timing phase control signal, simultaneously filters and downconverts the digitized signal to baseband, corrects timing phase misalignment between the digitized signal and the locally generated pseudo-noise sequence signal, and outputs a complex corrected baseband signal.

2. An apparatus for digitally downconverting and despreading an analog direct sequence spread spectrum signal as recited in claim 1, wherein an impulse response of the downconverter/polyphase filter is matched to a pulse shape of the spread spectrum signal.

3. An apparatus for digitally downconverting and despreading an analog direct sequence spread spectrum signal, comprising:

a free-running, non-steered, clock generator which outputs an A/D sample clock;

the A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal;

an A/D converter which receives the spread spectrum signal and the A/D sample clock and outputs a digitized signal from the spread spectrum signal;

a local pseudo-noise sequence signal generator which outputs a local pseudo-noise sequence signal;

a complex downconverter/polyphase filter which receives the digitized signal and the A/D sample clock and a sample timing phase control signal, simultaneously filters and downconverts the digitized signal to baseband, corrects timing phase misalignment between the digitized signal and the locally generated pseudo-noise sequence signal, and outputs a complex corrected baseband signal;

wherein an impulse response of the downconverter/polyphase filter is matched to a pulse shape of the spread spectrum signal;

a demultiplexer which receives the complex corrected baseband signal from the complex downconverter/polyphase filter and separates the complex corrected baseband signal into a complex punctual signal and a complex early/late signal and outputs the complex punctual and early/late signals;

wherein the complex punctual signal consists of samples of the complex corrected baseband signal detected at chip detection points; and

the complex early/late signal consists of samples of the corrected signal detected at chip transition points;

an early channel processor which receives the complex early/late signal, despreads and accumulates the complex early/late signal using the locally generated pseudo-noise sequence signal and outputs a complex early timing error signal;

a punctual channel processor which receives the complex punctual signal, delays the locally generated pseudo-noise sequence signal, despreads and accumulates the punctual signal using the delayed locally generated pseudo-noise sequence signal, and outputs a complex data symbol;

a late channel processor which receives the complex early/late signal, further delays the locally generated pseudo-noise sequence signal, relative to the delayed locally generated pseudo-noise sequence signal, despreads and accumulates the early/late signal using the further delayed locally generated pseudo-noise sequence signal and outputs a complex late timing error signal; and

a digital signal processor which receives the complex early timing error signal, the complex data symbol and the complex late timing error signal and performs coherent carrier frequency and phase tracking and MPSK demodulation on a complex data symbol and which outputs a demodulated data bit, sample timing phase control signal and filter coefficient values.

4. The apparatus as recited in claim 3 wherein the complex downconverter/polyphase filter further comprises:

a delay line which receives the digitized signal and the A/D sample clock;

a memory array storing coefficient data in a plurality of memory banks;

a plurality of multipliers, one per each memory bank, respectively, wherein each multiplier receives a tapped output from the delay line and selected coefficient data from the respective memory bank and outputs a product value;

an accumulator which receives the product value from each one of the plurality of multipliers and which outputs an accumulated value; and

a limiter/rounder circuit which receives the accumulated value and outputs a limited/rounded value;

wherein the selectable coefficient data from each memory bank is determined by the sample timing phase control signal.

5. An apparatus as recited in claim 3 wherein the demultiplexer comprises:

control logic which receives the A/D sample clock and generates a plurality of clock signals, each clock signal having a frequency equal to the chip rate of the spread spectrum signal and each clock signal offset in time with a next clock signal; and

a plurality of latches, one latch per each clock signal, respectively, each latch receiving the corrected baseband signal and the respective clock signal and outputting a demultiplexed signal.

6. An apparatus as recited in claim 4 wherein the demultiplexer comprises:

control logic which receives the A/D sample clock and generates a plurality of clock signals, each clock signal having a frequency equal to the chip rate of the spread spectrum signal and each clock signal offset in time with a next clock signal; and

a plurality of latches, one latch per each clock signal, respectively, each latch receiving the corrected baseband signal and the respective clock signal and outputting a demultiplexed signal.

7. The apparatus as recited in claim 3 wherein, the early channel processor comprises:

a first despreader which receives a real component of the complex early/late signal and the local pseudo-noise sequence signal and outputs a first despread signal;

a first accumulate and dump filter which receives the first despread signal and outputs a real (I) component of the complex early timing error signal;

a second despreader which receives an imaginary component of the complex early/late signal and the local pseudo-noise sequence signal and outputs a second despread signal;

a second accumulate and dump filter which receives the second despread signal and outputs an imaginary (Q) component of the complex early timing error signal; and

the punctual channel processor comprises;

a punctual delay element which receives the local pseudo-noise sequence signal and outputs a punctual delayed local pseudo-noise sequence signal;

a third despreader which receives a real component of the complex punctual signal and the punctual delayed local pseudo-noise sequence signal and outputs a third despread signal;

a third accumulate and dump filter which receives the third despread signal and outputs a real (I) component of the complex data symbol;

a fourth despreader which receives an imaginary component of the complex punctual signal and the delayed local pseudo-noise sequence signal and outputs a fourth despread signal;

a fourth accumulate and dump filter which receives the fourth despread signal and outputs an imaginary (Q) component of the complex data symbol; and

the late channel processor comprises;

a late delay element which receives the local pseudo-noise sequence signal and outputs a late delayed local pseudo-noise sequence signal;

a fifth despreader which receives the real component of the complex early/late signal and the late delayed local pseudo-noise sequence signal and outputs a fifth despread signal;

a fifth accumulate and dump filter which receives the fifth despread signal and outputs a real (I) component of the complex late timing error signal;

a sixth despreader which receives the imaginary component of the complex early/late signal and the late delayed pseudo-noise sequence signal and outputs a sixth despread signal; and

a sixth accumulate and dump filter which receives the sixth despread signal and outputs an imaginary (Q) component of the complex late timing error signal.

8. The apparatus as recited in claim 7 wherein:

(a) the first despreader comprises a first plurality of Exclusive-OR gates connected in parallel which each receive the local pseudo-noise sequence signal and the real component of the complex early/late signal;

(b) the first accumulate and dump filter comprises a first accumulator which receives an output from the first plurality of Exclusive-OR gates and outputs a first accumulated value; and

an early I output latch which latches and outputs the first accumulated value;

(c) the second despreader comprises a second plurality of Exclusive-OR gates connected in parallel each of which receives a second delayed local pseudo-noise sequence signal and the imaginary component of the complex early/late signal;

(d) the second accumulate and dump filter comprises a second accumulator which receives an output from the second plurality of Exclusive-OR gates and outputs a second accumulated value; and

an early Q output latch which latches and outputs the second accumulated value.

9. A method of digitally downconverting and despreading an analog direct sequence spread spectrum signal, comprising the steps of:

generating a free-running, non-steered, A/D sample clock;

the A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal;

converting the spread spectrum signal into a digitized signal using the A/D sample clock and outputting a digitized signal;

generating a local pseudo-noise sequence signal; and

simultaneously downconverting to baseband and filtering the digitized signal with a polyphase filter, correcting timing phase misalignment between the digitized signal and the locally generated pseudo-noise sequence signal and outputting a complex corrected baseband signal.

10. A method of digitally downconverting and despreading an analog direct sequence spread spectrum signal as recited in claim 9 wherein,

an impulse response of the polyphase filter is matched to a pulse shape of the spread spectrum signal.

11. A method of digitally downconverting and despreading an analog direct sequence spread spectrum signal, comprising the steps of:

generating a free-running, non-steered, A/D sample clock;

the A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal;

converting the spread spectrum signal into a digitized signal using the A/D sample clock and outputting a digitized signal;

generating a local pseudo-noise sequence signal;

simultaneously downconverting to baseband and filtering the digitized signal with a polyphase filter, correcting timing phase misalignment between the digitized signal and the locally generate pseudo-noise sequence signal and outputting a complex corrected baseband signal;

separating the complex corrected baseband signal into a complex punctual signal and a complex early/late signal;

outputting the complex punctual and early/late signals;

the complex punctual signal consisting of samples of the complex corrected baseband signal detected at chip detection points; and

the complex early/late signal consisting of samples of the complex corrected baseband signal detected at chip transition points;

despreading and accumulating the complex early/late signal using the locally generated pseudo-noise sequence signal and outputting a complex early timing error signal;

delaying the locally generated pseudo-noise sequence signal, despreading and accumulating the complex punctual signal using the delayed locally generated pseudo-noise sequence signal, and outputting a complex data symbol;

further delaying the locally generated pseudo-noise sequence signal, relative to the delayed locally generated pseudo-noise sequence signal, despreading and accumulating the complex early/late signal using the further delayed locally generated pseudo-noise sequence signal and outputting a complex late timing error signal; and

performing coherent carrier frequency and phase tracking and MPSK demodulation on said complex data symbol and outputting a demodulated data bit, sample timing phase control signal and filter coefficient values.

12. A method of digitally downconverting and despreading an analog direct sequence spread spectrum signal as recited in claim 11 wherein,

an impulse response of the polyphase filter is matched to a pulse shape of the spread spectrum signal.

13. An apparatus for digitally downconverting and despreading an analog direct sequence spread spectrum signal, comprising:

a clock generating means for generating and outputting a free-running, non-steered, A/D sample clock;

the A/D sample clock having a rate which is an integral multiple of a chip rate of the spread spectrum signal;

an A/D converting means for receiving the spread spectrum signal and the A/D sample clock and outputting a digitized signal from the spread spectrum signal;

a local pseudo-noise sequence signal generating means for generating and outputting a local pseudo-noise sequence signal;

a complex downconverter/polyphase filtering means for receiving the digitized signal and the A/D sample clock and a sample timing phase control signal, simultaneously filtering and downconverting the digitized signal to baseband, correcting timing phase misalignment between the digitized signal and the locally generated pseudo-noise sequence signal, and outputting a complex corrected baseband signal;

wherein an impulse response of the downconverter/polyphase filter is matched to a pulse shape of the spread spectrum signal;

a demultiplexing means for receiving the complex corrected baseband signal from the complex downconverter/polyphase filter and separating the complex corrected baseband signal into a complex punctual signal and a complex early/late signal and outputting the complex punctual and early/late signals;

wherein the complex punctual signal consists of samples of the complex corrected baseband signal detected at chip detection points; and

the complex early/late signal consists of samples of the complex corrected baseband signal detected at chip transition points;

an early channel processing means for receiving the complex early/late signal, despreading and accumulating the complex early/late signal using the locally generated pseudo-noise sequence signal and outputting a complex early timing error signal;

a punctual channel processing means for receiving the complex punctual signal, delaying the locally generated pseudo-noise sequence signal, despreading and accumulating the complex punctual signal using the delayed locally generated pseudo-noise sequence signal, and outputting a complex data symbol;

a late channel processing means for receiving the complex early/late signal, further delaying the locally generated pseudo-noise sequence signal, relative to the delayed locally generated pseudo-noise sequence signal, despreading and accumulating the complex early/late signal using the further delayed locally generated pseudo-noise sequence signal and outputting a complex late timing error signal; and

a digital signal processing means for receiving the complex early timing error signal, the complex data symbol and the complex late timing error signal and performing coherent carrier frequency and phase tracking and MPSK demodulation on a complex data symbol and outputting a demodulated data bit, sample timing phase control signal and filter coefficient values.