Direct conversion receiver

• US 5,640,428 A
• Filed: 11/09/1995
• Issued: 06/17/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mimura, Masahiro, Hasegawa, Makoto, Abe, Katsuaki, Watanabe, Kazunori, Yokozaki, Katsushi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US08/555,407
• Time in Patent Office: 586 Days
• Field of Search: 375/334, 375/324, 375/328, 375/272, 329/315, 329/327, 329/343, 329/303, 329/300
• US Class Current: 375/334
• CPC Class Codes: H04L 27/1525 using quadrature demodulation

Abstract

In a first direct conversion receiver for demodulating I and Q signals, having a quadrature relation therebetween, obtained from a received FSK signal through a direct conversion, a first D FF latches a level of the I signal when a sign condition of I and Q signals moves from the same to different sign conditions, a second D FF latches a level of the Q signal when the sign condition of the I and Q signals moves from the different to same sign condition and EXCLUSIVE OR operations are made among the I and Q signals and the outputs of the first and second D FFs to provide a frequent data judgement to improve a receiving sensitivity of an FSK signal having a relative low modulation index. In a second direct conversion receiver, a sign change in the Q signal is detected by a first edge detection circuit 17, a first D FF holds the level of the I signal, and an EXCLUSIVE OR circuit provides a first demodulation result. A sign change in the I signal is detected by a second edge detection circuit 17, a second D FF holds the level of the Q signal, an EXCLUSIVE OR circuit provides a second demodulation result and a subtracting circuit combines the first and second demodulation results. An earlier change detection circuit also combines the first and second demodulation results with a delay in the first and second demodulation results reduced.

Claims

1. A direct conversion receiver for demodulating first and second digital signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first EXCLUSIVE OR circuit (114) for effecting a first EXCLUSIVE OR operation between said first and second digital signals;

a first D flip flop circuit (118) for holding a level of said first digital signal in response to a rising edge of an output of the first EXCLUSIVE OR circuit;

a second D flip flop circuit (119) for holding a level of said second digital signal in response to a falling edge of said output of the first EXCLUSIVE OR circuit;

a second EXCLUSIVE OR circuit (115) for effecting a second EXCLUSIVE OR operation between said first digital signal and an output of said second D flip flop circuit;

a third EXCLUSIVE OR circuit (116) for effecting a third EXCLUSIVE OR operation between said second digital signal and an output of said first D flip flop circuit; and

a fourth EXCLUSIVE OR circuit (117) for effecting a fourth EXCLUSIVE OR operation between outputs of said second and third EXCLUSIVE OR circuits to output a demodulation result.

2. A direct conversion receiver as claimed in claim 1, further comprising a low pass filter (121) for low-pass filtering said demodulation result.

6. A direct conversion receiver as claimed in claim 1, wherein said frequency shift keying signal is subjected to multi-value frequency shift keying, said direct conversion receiver, further comprising:

a frequency to a voltage converting circuit (802); and

a comparing circuit (803) for comparing an output of said voltage converting circuit with at least a reference voltage and outputting another demodulation result, said demodulation result and said another demodulation result providing demodulation of said multi-value frequency shift keying.

3. A direct conversion receiver for demodulating first and second digital signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first EXCLUSIVE OR circuit (114) for effecting a first EXCLUSIVE OR operation between said first digital signal and said second digital signal;

a D flip flop circuit (118) for holding a level of said first digital signal in response to a rising edge of an output of the first EXCLUSIVE OR circuit;

a second EXCLUSIVE OR circuit (117) for effecting a second EXCLUSIVE OR operation between an output of said D flip flop circuit and said second digital signal;

a low pass filter circuit (121) for integrating an output of the fourth EXCLUSIVE OR circuit; and

a high pass filter circuit (402) for removing a dc component from an output of the low pass filter circuit and outputting a demodulation result.

4. A direct conversion receiver for demodulating first and second digital signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first EXCLUSIVE OR circuit (114) for effecting a first EXCLUSIVE OR operation between said first and second digital signals;

a D flip flop circuit (119) for holding a level of said second digital signal in response to a falling edge of an output of the first EXCLUSIVE OR circuit;

a second EXCLUSIVE OR circuit (117) for effecting a second EXCLUSIVE OR operation between an output of said D flip flop circuit and said first digital signal;

a low pass filter circuit (121) for integrating an output of said second EXCLUSIVE OR circuit; and

a high pass filter circuit (402) for removing a dc component from an output of the low pass filter circuit and outputting a demodulation result.

5. A direct conversion receiver for demodulating first and second analog signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first multiplier (601) for multiplying said first analog signal with said second analog signal;

a first delay circuit (607) for delaying an output of said first multiplier by a delay time corresponding to π

/4 of a deviation frequency of said received frequency shift keying signal;

a first holding circuit (605) for holding a level of said first analog signal when a polarity of an output of said first delay circuit changes from a negative polarity to a positive polarity;

a second holding circuit (606) for holding a level of said second analog signal when a polarity of an output of said first delay circuit changes from a positive polarity to a negative polarity;

a second delay circuit (608) for delaying said first analog signal by said delay time;

a third delay circuit (609) for delaying said second analog signal by said delay time;

a second multiplier (602) for multiplying an output of said second delay circuit with an output of said second holding circuit;

a third multiplier (603) for multiplying an output of said third delay circuit with an output of said first holding circuit;

a fourth multiplier (604) for multiplying an output of said second multiplier with an output of said third multiplier; and

a low pass filter (610) for removing a dc component from an output of said fourth multiplier to provide a demodulation result.

7. A direct conversion receiver for demodulating first and second digital signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first edge detection circuit (17) for detecting an edge in said second digital signal;

a first holding circuit (18) for holding a level of the first digital signal in response to an output of said edge detection circuit;

a first EXCLUSIVE OR circuit (20) for effecting an EXCLUSIVE OR operation between said second digital signal and an output of said holding circuit to provide a first demodulation result;

a second edge detection circuit (23) for detecting an edge in said first digital signal;

a second holding circuit (24) for holding a level of the second digital signal in response to an output of said second edge detection circuit;

an EXCLUSIVE OR circuit (26) for effecting an EXCLUSIVE OR operation between said first digital signal and an output of said second holding circuit to provide a second demodulation result; and

a subtracting circuit for effecting a subtraction between said first demodulation result and said second demodulation result.

8. A direct conversion receiver for demodulating first and second digital signals, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion comprising:

a first edge detection circuit (17) for detecting an edge in said second digital signal;

a first holding circuit (18) for holding a level of the said first digital signal in response to an output of said first edge detection circuit;

a first EXCLUSIVE OR circuit (20) for effecting a first EXCLUSIVE OR operation between said second digital signal and an output of said first holding circuit to provide a first demodulation result;

a second edge detection circuit (23) for detecting an edge in said first digital signal;

a second holding circuit (24) for holding a level of the said second digital signal in response to an output of said second edge detection circuit;

a second EXCLUSIVE OR circuit (26) for effecting a second EXCLUSIVE OR operation between said first digital signal and an output of said second holding circuit to provide a second demodulation result, either said first demodulation result leading said second demodulation result by a phase difference between said first and second digital signals or said second demodulation result leading said first demodulation result by said phase;

an earlier change detection circuit for detecting a change in said first and second demodulation results and outputting a third demodulation result such that when said first demodulation result leads said second demodulation result by said phase difference, said earlier change detection circuit outputs said first demodulation result as a third demodulation result and when said second demodulation result leads said first demodulation result by said phase difference, said earlier change detection circuit outputs said second demodulation result as said second demodulation result.

9. A direct conversion receiver as claimed in claim 8, wherein said earlier change detection circuit comprising:

a first inverter (30) for inverting said second demodulation result;

a third EXCLUSIVE OR circuit (45) for effecting a third EXCLUSIVE OR operation between said first demodulation result and an output of said first inverter;

a second inverter (46) for inverting an output of said third EXCLUSIVE OR circuit;

a third holding circuit (47) for holding said first demodulation result in response to an output of said second inverter; and

a fourth EXCLUSIVE OR circuit (48) for effecting a fourth EXCLUSIVE OR operation between an output of said holding circuit and said output of said third EXCLUSIVE OR circuit.

10. A direct conversion receiver for demodulating digital in-phase and quadrature signals and second, having a quadrature relation therebetween, obtained from a received frequency shift keying signal through a direct conversion, comprises:

sign change detection means for detecting a sign condition of said digital in-phase and quadrature signals;

a first D flip flop circuit for latching a level of said digital in-phase signal when a sign condition of said digital in-phase and quadrature signals moves from the same to different sign conditions;

a second D flip flop circuit for latching a level of said quadrature signal when said sign condition of said digital in-phase and quadrature signals moves from a different to the same sign conditions; and

an EXCLUSIVE OR circuit for effecting EXCLUSIVE OR operations among said digital in-phase and quadrature signals to provide a demodulation result.