Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length

• US 5,640,518 A
• Filed: 01/18/1996
• Issued: 06/17/1997
• Est. Priority Date: 12/14/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arroyo, Ronald Xavier, Muhich, John Stephen, Wright, Charles Gordon, Merkel, Lawrence Joseph
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/588,150
• Time in Patent Office: 516 Days
• Field of Search: 395/800, 395/200.05, 395/200.13, 395/200.14, 395/285, 395/286, 395/287, 395/290, 395/856, 395/860, 395/741, 395/476, 395/478, 395/855
• US Class Current: 710/110
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/30 with priority control
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system'"'"'s bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

Claims

1. In a microprocessor bus interface servicing a plurality of processors on a system bus and having a turnaround cycle between a current tenure and a next tenure on said bus, each of said tenures serving a respective master device and a respective slave device, said turnaround cycle being provided to allow the current master and slave to restore control signals and exit the system bus so as to avoid bus contention problems, a method of eliminating said turnaround cycle between successive data bus tenures, comprising the steps of:

arbitrating for mastership of the system bus and granting the bus to a master for data transfer between the master and a slave during a bus tenure, the slave normally generating a data termination signal for each data beat in a data transfer;

asserting a single pre-last transfer acknowledge signal by the slave one cycle before a last transfer acknowledge signal; and

granting the data bus to a next master on a cycle following assertion of the pre-last transfer acknowledge in cases where bus turnaround may be eliminated without creating bus contention problems between said previous and current data tenures, such cases being where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures, thereby eliminating the bus turnaround cycle and effectively increasing the data bus bandwidth.

2. The method recited in claim 1 further comprising the step of transferring data from a system memory to a microprocessor when the microprocessor is the master of the system bus.

3. The method recited in claim 2 further comprising the step of continuing the bus tenure with each read transfer by broadcasting a next address in memory until the system memory asserts the pre-last transfer acknowledge, effectively executing a burst read tenure initially having an unknown length.

4. The method recited in claim 1 further comprising the step of transferring data from a microprocessor to a system memory when the microprocessor is the master of the system bus.

5. The method recited in claim 4 further comprising the step of continuing the bus tenure with each write transfer by broadcasting a next address in memory until the microprocessor asserts the pre-last transfer acknowledge, effectively executing a burst write tenure initially having an unknown length.

6. A computer system comprising:

a system bus and an arbiter connected to said system bus;

a plurality of devices connected to said system bus including at least one microprocessor, a system memory and an input/output channel, said arbiter arbitrating mastership of the system bus and granting the bus to a master for data transfer between the master and a slave during a bus tenure;

said at least one microprocessor having a system interface connected to the system bus for transferring data between the microprocessor and or said system memory and said input/output channel via the system bus; and

said system interface including signalling means for normally generating a data termination signal for each data beat in a data transfer, a transfer acknowledge signal asserted by a responding slave indicating normal termination of data transactions, and optionally asserting a single pre-last transfer acknowledge signal by the slave one cycle before a last transfer acknowledge signal is asserted, said arbiter receiving said pre-last transfer acknowledge signal and granting the system bus to the master for a next data tenure eliminating a bus turnaround cycle in cases where bus turnaround may be eliminated without creating bus contention problems between said previous and current data tenures, such cases being where the same slave is involved in consecutive read data bus tenures or when the same master and slave are involved in data bus write tenures, thereby eliminating the bus turnaround cycle and effectively increasing the data bus bandwidth.

7. In a microprocessor bus interface having one or more bus cycles of dead time between data tenures on said bus, said cycles providing data bus turnaround between a previous data tenure and a current data tenure, each of said tenures having a respective master device and a respective slave device, said turnaround allowing said previous master and slave to restore control signals and get off the system bus so as to avoid bus contention problems, a method of eliminating said turnaround between successive read tenures involving the same slave or successive write tenures involving the same master and slave, comprising the steps of:

asserting a pre-last transfer acknowledge signal by said previous slave one cycle before said slave asserts a last transfer acknowledge signal, said last transfer acknowledge signal normally signalling termination of said previous data tenure;

determining whether said previous and current data tenures are such that said turnaround may be eliminated without creating bus contention problems between said previous and current data tenures;

eliminating said turnaround by using said pre-last transfer acknowledge signal of said previous slave to signal termination of said previous data tenure.

8. The method recited in claim 7 further comprising the step of transferring data from a system memory to a microprocessor when the microprocessor is the master of the system bus.

9. The method recited in claim 8 further comprising the step of continuing the bus tenure with each read transfer by broadcasting a next address in memory until the system memory asserts the pre-last transfer acknowledge, effectively executing a burst read tenure initially having an unknown length.

10. The method recited in claim 7 further comprising the step of transferring data from a microprocessor to a system memory when the microprocessor is the master of the system bus.

11. The method recited in claim 10 further comprising the step of continuing the bus tenure with each write transfer by broadcasting a next address in memory until the microprocessor asserts the pre-last transfer acknowledge, effectively executing a burst write tenure initially having an unknown length.