Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery

• US 5,640,523 A
• Filed: 02/07/1996
• Issued: 06/17/1997
• Est. Priority Date: 09/02/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Bertrand J.
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Shankar, Vijay
• Application Number:
  US08/598,157
• Time in Patent Office: 496 Days
• Field of Search: 375/238, 375/340, 375/359, 375/360, 375/348, 375/371, 375/374, 375/375, 375/376, 327/7, 327/8, 327/10, 327/12, 327/144, 327/147, 327/148, 327/149, 327/153, 327/161, 327/236
• US Class Current: 375/360
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase detector detects a transition edge on a received data signal and generates a pump-down reference pulse and a pump-up, variable width pulse indicative of phase to synchronize a local clock with the received data signal. The variable width pulse overlaps in time with the reference pulse. The reference pulse is subtracted from the variable width pulse, and the resulting difference signal is supplied in an integrated format to a voltage controlled oscillator (VCO) that controls the frequency of the local clock. When the phase detector is balanced, the variable width pulse and the reference pulse substantially cancel out one another, providing for relatively reduced jitter for the local clock.

Claims

1. A method for outputting a variable width pulse indicative of phase and a reference pulse as phase detector outputs, comprising the steps of:

(a) receiving a first data signal having a first transition edge;

(b) detecting the first transition edge of the first data signal;

(c) outputting a reference pulse in response to the detection of the first transition edge of the first data signal and in accordance with a first clock edge and a second clock edge; and

(d) outputting a variable width pulse indicative of phase in response to the detection of the first transition edge of the first data signal such that the variable width pulse overlaps in time with the reference pulse, and the variable width pulse and the reference pulse substantially cancel out one another when the phase detector is balanced, further wherein the step of outputting a variable width pulse includes the steps of;

(i) delaying the first data signal for a period of time to produce a delayed data signal having a second transition edge delayed from the first transition edge in the first data signal,

ii) detecting the second transition edge of the delayed data signal, and

(iii) outputting the variable width pulse indicative of phase in response to the detection of the second transition edge of the delayed data signal and in accordance with the second clock edge.

2. The method of claim 1, wherein the detecting step (b) includes the steps of:

(i) retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and

(ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal.

3. The method of claim 2, wherein the outputting step (c) includes the steps of:

(i) retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal,

(ii) retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and

(iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

4. The method of claim 1, wherein the delaying step (d)(i) includes the step of delaying the first data signal for a period of time equal to approximately one-half of a clock period for transmitting the first data signal.

5. The method of claim 1, wherein the detecting step (b) includes the steps of:

(i) retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and

(ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and

wherein the outputting step (c) includes the steps of;

(i) retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal,

(ii) retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and

(iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

6. The method of claim 1, wherein the detecting step (d)(ii) and the outputting step (d)(iii) include the steps of:

(A) retiming the delayed data signal in accordance with a first clock edge to produce a first retimed data signal, and

(B) exclusive ORing the delayed data signal with the first retimed data signal to output the variable width pulse.

7. The method of claim 6, wherein the detecting step (b) includes the steps of:

(i) retiming the first data signal in accordance with a second clock edge to produce a first retimed data signal, and

(ii) exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and

wherein the outputting step (c) includes the steps of;

(i) retiming the second data signal in accordance with the second clock edge to produce a second retimed data signal,

(ii) retiming the second retimed data signal in accordance with first clock edge to produce a third retimed data signal, and

(iii) exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

8. A phase detector for outputting a variable width pulse indicative of phase and a reference pulse, comprising:

(a) first circuitry for receiving a first data signal having a first transition edge and for detecting the first transition edge of the first data signal;

(b) second circuitry, coupled to the first circuitry, for outputting a reference pulse in response to the detection of the first transition edge of the first data signal and in accordance with a first clock edge and a second clock edge; and

(c) third circuitry, coupled to the first circuitry, for outputting a variable width pulse indicative of phase in response to the detection of the first transition edge of the first data signal, the third circuitry outputting the variable width pulse such that the variable width pulse overlaps in time with the reference pulse, and the variable width pulse and the reference pulse substantially cancel out one another when the phase detector is balanced, further wherein the third circuitry includes;

(i) delay circuitry for delaying the first data signal for a period of time to produce a delayed data signal having a second transition edge,

(ii) detection circuitry for detecting the second transition edge of the delayed data signal, and

(iii) output circuitry for outputting the variable width pulse indicative of phase in response to the detection of the second transition edge of the delayed data signal and in accordance with the second clock edge such that the reference pulse and the variable width pulse are aligned along the second clock edge.

9. The phase detector of claim 8, wherein the first circuitry (a) includes:

(i) circuitry for retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and

(ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal.

10. The phase detector of claim 9, wherein the second circuitry (b) includes:

(i) circuitry for retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal,

(ii) circuitry for retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and

(iii) an exclusive OR gate for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

11. The phase detector of claim 8, wherein the delay circuitry (c)(i) delays the first data signal for a period of time equal to approximately one-half of a clock period for transmitting the first data signal.

12. The phase detector of claim 8, wherein the first circuitry (a) includes:

(i) circuitry for retiming the first data signal in accordance with a first clock edge to produce a first retimed data signal, and

(ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and

wherein the second circuitry (b) includes;

(i) circuitry for retiming the second data signal in accordance with the first clock edge to produce a second retimed data signal,

(ii) circuitry for retiming the second retimed data signal in accordance with a second clock edge to produce a third retimed data signal, and

(iii) an exclusive OR gate for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.

13. The phase detector of claim 8, wherein the detection circuitry (c)(ii) and the output circuitry (c)(iii) include:

(A) circuitry for retiming the delayed data signal in accordance with a first clock edge to produce a first retimed data signal, and

(B) an exclusive OR gate for exclusive ORing the delayed data signal with the first retimed data signal to output the variable width pulse.

14. The phase detector of claim 13, wherein the first circuitry (a) includes:

(i) circuitry for retiming the first data signal in accordance with a second clock edge to produce a first retimed data signal, and

(ii) an exclusive OR gate for exclusive ORing the first retimed data signal with the first data signal to produce a second data signal indicative of the first transition edge of the first data signal; and

wherein the second circuitry (b) includes;

(i) circuitry for retiming the second data signal in accordance with the second clock edge to produce a second retimed data signal,

(ii) circuitry for retiming the second retimed data signal in accordance with first clock edge to produce a third retimed data signal, and

(iii) circuitry for exclusive ORing the second retimed data signal with the third retimed data signal to output the reference pulse.