IC analysis system having charged particle beam apparatus for improved contrast image

• US 5,640,539 A
• Filed: 09/21/1994
• Issued: 06/17/1997
• Est. Priority Date: 09/21/1993
• Status: Expired due to Fees

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Kurihara, Masayuki, Ueda, Koshi, Goishi, Akira
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/309,750
• Time in Patent Office: 1,000 Days
• Field of Search: 395/500, 382/141, 382/144, 382/145, 382/147, 364/491, 371/27, 371/22.3, 371/22.5, 371/22.6, 324/158.1, 324/751, 250/310, 250/306, 250/396 R, 250/397, 250/398, 250/492.2, 250/492.3
• US Class Current: 250/310
• CPC Class Codes: G01R 31/307 of integrated circuits

Abstract

The object of the invention is to provide an IC analysis system having a charged particle beam apparatus in which the operability and picture quality have been enhanced and the measurement method of a device under test. In the IC analysis system, stop signal generating means in which the stop signal stimulates the acquisition of image data is added to a test pattern generator and acquisition completion signal generating means which releases the stopping state on completing the acquisition of image data and which resumes the test pattern updating operation is added to the charged particle beam apparatus. Furthermore, by adding mode select means to the charged particle beam apparatus, a clearer potential contrast image can be obtained. The methods for locating fault positions can be realized in the IC analysis system having the charged particle beam apparatus wherein the image data can be obtained by alternate test patterns, or by adding one image data to the reverse potential of another image data, or by scanning and irradiating the charged particle beam onto the same surface of the device at a plurality of times.

Claims

1. An integrated circuit (IC) analysis system (100), comprising:

an ion beam tester (300) which irradiates and scans an ion beam on the surface of a device under test, measures the amount of secondary electrons at each irradiated point, and displays the surface potential distribution of said device under test as an image;

a test pattern generator (200) which sequentially updates and applies test patterns to said device under test;

stop pattern setting means (203) for setting at least two stop patterns of a first test pattern and a second test pattern to suspend test pattern updating operations of said test pattern generator (200);

pattern holding means (204) for suspending test pattern updating operations while keeping said test pattern generator (200) generating said first or second test pattern set by said stop pattern setting means (203), and resuming test pattern updating operations when receiving from said ion beam tester (300) an acquisition completion signal representing the completion of acquisition of image data;

stop signal generating means (205) for generating a stop signal representing the suspension of test pattern updating operations;

image data acquisition means (305) in said ion beam tester (300) for responding said stop signal from said stop signal generating means (205) to resume acquisition of said image data; and

mode select means (309) in said ion beam tester (300) for executing either a first mode operation in which, when said first test pattern is generated and test pattern updating operations are suspended, said device under test is irradiated with an ion beam scanning, but acquisition of image data is prohibited, or a second mode operation in which, when said second test pattern is generated and test pattern updating operations are suspended, said device under test is irradiated with an ion beam scanning, and acquisition of image data is performed.

2. An IC analysis system (100) according to claim 1, wherein said ion beam tester (300) includes acquisition completion signal generating means (308) which generates said acquisition completion signal representing that said image data acquisition means (305) has completed acquisition of said image data, and wherein said pattern holding means (204) controls said test pattern generator (200) to resume said test pattern updating operations in response to said acquisition completion signal from said ion beam tester (300).

3. An ion beam tester (300) which irradiates a scanning ion beam on the surface of a device under test, said device under test being applied with sequentially updated and generated test patterns from a test pattern generator (200), said ion beam tester (300) measures the amount of secondary electrons at each irradiated point and displays the surface potential distribution of said device under test as an image, said ion beam tester comprising:

image data acquisition means (305) for responding to a stop signal from said test pattern generator (200) to resume acquisition of image data;

mode select means (309) for executing either a first mode operation in which, when said first test pattern is generated and test pattern updating operations are suspended, said device under test is irradiated with an ion beam scanning, but acquisition of image data is prohibited, or a second mode operation in which, when said second test pattern is generated and test pattern updating operations are suspended, said device under test is irradiated with an ion beam scanning, and acquisition of image data performed.

4. An ion beam tester (300) according to claim 3, said ion beam tester further includes acquisition completion signal generating means (308) which generates an acquisition completion signal representing that said image data acquisition means (305) has completed acquisition of said image data, and provides said acquisition completion signal to said test pattern generator (200).

5. A fault isolation method used in an IC analysis system (100) composed of a charged particle beam apparatus (300) which irradiates a charged particle beam scanning on the surface of a device under test, measures the amount of secondary electrons at each irradiated point, and displays the surface potential distribution of said device under test as an image, a test pattern generator (200) which sequentially updates and applies test patterns to said device under test, and stop pattern setting means (203) in which stop patterns of a first test pattern and a second test pattern can be set, said method comprising the steps of:

setting the same pattern n as said first and second test patterns, and setting different operation conditions between said first and second test patterns for said device under test, said different operation conditions including voltage or frequency differences between said first and second test patterns;

performing irradiation with a charged particle beam scanning without performing acquisition of image data when said first test pattern n is generated;

performing both irradiation with a charged particle beam scanning and acquisition of image data when said second test pattern n is generated;

displaying said surface potential contrast image of said device under test.

8. A fault isolation method according to claims 5, 6, or 7, wherein said charged particle beam (300) is an ion beam tester.

9. A fault isolation method according to claims 5, 6, or 7, wherein said charged particle beam apparatus (300) is an electron beam tester.

6. A fault isolation method used in an IC analysis system (100) composed of a charged particle beam apparatus (300) which irradiates the surface of a device under test a charge particle beam scanning, measures the amount of secondary electrons at each irradiated point, and displays the surface potential distribution of said device under test as an image, a test pattern generator (200) which sequentially updates and applies test patterns to said device under test, and has stop pattern setting means (203) in which two stop patterns of a first test pattern and a second test pattern can be set, said method comprising the steps of:

setting pattern r as said first test pattern and pattern n as said second test pattern, said second test pattern having opposite potentials to that of said first test pattern with respect to circuit components in said device under test;

performing both irradiation with a charged particle beam scanning and acquisition of image data when said first test pattern r is generated;

performing both irradiation with a charged particle beam scanning and acquisition of image data when said second test pattern n is generated;

calculating the difference between the image data acquired when said first test pattern r is provided to said device under test and said second test pattern n is provided to said device under test;

displaying said surface potential contrast image of said device under test.

7. A fault isolation method used in an IC analysis system (100) composed of a charged particle beam apparatus (300) which irradiates the surface of a device under test a charge particle beam scanning, measures the amount of secondary electrons at each irradiated point, and displays the surface potential distribution of said device under test as an image, a test pattern generator (200) which sequentially updates and applies test patterns to said device under test, and has stop pattern setting means (203) in which two stop patterns of a first test pattern and a second test pattern can be set, comprising the steps of:

setting pattern r as said first test pattern and pattern n as said second test pattern, said second test pattern having opposite potentials to that of said first test pattern with respect to circuit components in said device under test;

irradiating an area of said device under test displayed on a monitor two or more times with a charged particle beam scanning when said first test pattern r is applied to said device under test;

irradiating the area displayed on said monitor two or more times with a charged particle beam scanning when said second test pattern n is is applied to said device under test;

acquiring only one image data when irradiating said charged particle beam scanning on said device under test during said application of either said first test pattern r or said second test pattern n to said device under test; and

displaying said surface potential contrast image of said device under test based on said one image data.