Register stacking in a computer system
First Claim
1. A computer comprising:
- a central processing unit (CPU) for executing instructions, each instruction having register identifying bits;
a plurality of register stacks, each register stack including;
a general purpose register switchably coupled to said CPU;
at least one auxiliary register switchably coupled to said CPU, each general purpose register and each auxiliary register occupying a corresponding register stack level of said register stack, both said general purpose register and said at least one auxiliary register within the same stack being identified by the same value residing in said register identifying bits;
selection circuitry including at least one programmable storage element, each storage element for storing a register stack level pointer, said pointer for selecting either a general purpose register or an auxiliary register at a corresponding level within at least one stack, wherein said register stack level pointer is controlled solely through execution of at least one register stack operation; and
switching circuitry for switching, for each register stack, between a first data path from said CPU to said general purpose register or a second data path from said CPU to one of said at least one auxiliary registers depending upon the register selection by said selection circuitry.
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Abstract
A computer system provides an expanded register set by employing transparent register stacks for each general purpose register. Each general purpose register and its corresponding set of auxiliary registers form a register stack. No register identification bits are required in processor instructions to reference auxiliary registers. A register set select storage area is a programmable register provided for the storage of a value that identifies the currently active register level. The register set select storage area is loaded using two additional processor instructions provided as part of the present invention. A register set switch is used for selecting a data path to the register level specified by the register set select storage area. A PUSHREG instruction is used to push the register stack pointer down one level. A POPREG instruction is used to move the register stack pointer up one register level. In a alternative embodiment of the present invention, the POPREG and PUSHREG instructions include an argument that specifies the single register stack that is manipulated. In another embodiment of the present invention, register stack underflow or overflow conditions are trapped using an interrupt process. Task switching is implemented with the present invention using a plurality of register stacks each associated with a task frame. In another embodiment of the present invention, the semantics of interrupts to the processor are changed to include an automatic PUSHREG and POPREG instruction execution.
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Citations
20 Claims
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1. A computer comprising:
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a central processing unit (CPU) for executing instructions, each instruction having register identifying bits; a plurality of register stacks, each register stack including; a general purpose register switchably coupled to said CPU; at least one auxiliary register switchably coupled to said CPU, each general purpose register and each auxiliary register occupying a corresponding register stack level of said register stack, both said general purpose register and said at least one auxiliary register within the same stack being identified by the same value residing in said register identifying bits; selection circuitry including at least one programmable storage element, each storage element for storing a register stack level pointer, said pointer for selecting either a general purpose register or an auxiliary register at a corresponding level within at least one stack, wherein said register stack level pointer is controlled solely through execution of at least one register stack operation; and switching circuitry for switching, for each register stack, between a first data path from said CPU to said general purpose register or a second data path from said CPU to one of said at least one auxiliary registers depending upon the register selection by said selection circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer comprising:
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a central processing unit (CPU) for executing instructions, each instruction having register identifying bits; a plurality of register stacks, each register stack including; a general purpose register switchably coupled to said CPU; at least one auxiliary register switchably coupled to said CPU, each general purpose register and each auxiliary register occupying a corresponding register stack level of said register stack, both said general purpose register and said at least one auxiliary register within the same stack being identified by the same value residing in said register identifying bits; selection circuitry including at least one programmable storage element, each storage element for storing a register stack level pointer, said pointer for selecting an auxiliary register at a corresponding level within at least one stack, wherein said register stack level pointer is controlled solely through execution of at least one register stack operation; and swapping circuitry for swapping the contents of a general purpose register and an auxiliary register within a register stack when the auxiliary register is selected by said selection circuitry, and for swapping back the contents of the general purpose register and a previously selected auxiliary register in response to the auxiliary register being selected by said selection circuitry, wherein the auxiliary register, the previously selected auxiliary register, and the general purpose register are within the same register stack.
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11. In a computer having a central processing unit (CPU), said CPU for executing an instruction in an instruction stream, said instruction having register identifying bits, the CPU further including a plurality of register stacks, each register stack having a general purpose register switchably coupled to said CPU and at least one auxiliary register switchably coupled to said CPU, each general purpose register and each auxiliary register occupying a corresponding register stack level of said register stack, both said general purpose register and said at least one auxiliary register within the same stack being identified by the same value residing in said register identifying bits, a process for accessing a register, said process comprising the steps of:
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executing at least one register stack operation to manipulate at least one register stack level pointer; selecting either said general purpose register or one of said at least one auxiliary registers at a corresponding level within at least one register stack solely according to said pointer manipulated by said at least one register stack operation; for each register stack, switching between a first data path from said CPU to said general purpose register or a second data path from said CPU to one of said at least one auxiliary registers depending upon the register selection made in said selecting step; and accessing a register identified by said register identifying bits. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. In a computer having a central processing unit (CPU), said CPU for executing an instruction in an instruction stream, said instruction having register identifying bits, the CPU further including a plurality of register stacks, each register stack having a general purpose register switchably coupled to said CPU and at least one auxiliary register switchably coupled to said CPU, each general purpose register and each auxiliary register occupying a corresponding register stack level of said register stack, both said general purpose register and said at least one auxiliary register within the same stack being identified by the same value residing in said register identifying bits, a process for accessing a register, said process comprising the steps of:
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executing at least one register stack operation to manipulate at least one register stack level pointer; selecting one of said at least one auxiliary registers at a corresponding level within at least one register stack solely according to said pointer manipulated by said at least one register stack operation; accessing a register identified by said register identifying bits; and swapping the contents of a general purpose register and an auxiliary register within a register stack when the auxiliary register is selected in said selecting step, and swapping back the contents of the general purpose register and a previously selected auxiliary register in response to the auxiliary register being selected, wherein the auxiliary register, the previously selected auxiliary register, and the general purpose register are within the same register stack.
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Specification