Storage controller and bus control method for use therewith

• US 5,640,600 A
• Filed: 01/31/1995
• Issued: 06/17/1997
• Est. Priority Date: 02/09/1994
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamamoto, Akira, Takeuchi, Hisaharu, Satoh, Takao, Inoue, Yasuo
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/381,560
• Time in Patent Office: 868 Days
• Field of Search: 395/834, 395/853, 395/854, 395/880, 395/200.13, 395/200.03, 395/200.06, 395/200.08, 395/200.11, 395/287, 395/293, 395/308, 395/299, 395/650, 395/438 , 395/440, 395/849, 395/494, 395/497.01, 395/306, 395/550, 395/750
• US Class Current: 710/33
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches

Abstract

A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.

Claims

1. A storage controller connected between a processor and a storage device for controlling data transfer therebetween, comprising:

a storage device adapter for controlling said storage device;

a cache memory for storing part of the data held in said storage device;

a channel adapter for communicating with said processor and for processing input/output requests received from said processor;

a control memory for storing control information used for communication between said storage device adapter and said channel adapter;

a plurality of buses each connected to at least two of said storage device adapter, said cache memory, said channel adapter and said control memory to transfer data and control information;

bus load estimating means for obtaining an index for bus load characteristics indicating a proportion of data transfer and control information transfer on said plurality of buses;

bus mode selecting means for selecting one of a plurality of a bus mode that determines utilization of said buses based on the index obtained by said bus load estimating means; and

each of said storage device adapter having bus access means and said channel adapter, for accessing said buses in accordance with the bus mode selected by said bus mode selecting means;

wherein said bus load estimating means includes sequential access residual byte detection means for detecting the residual bytes of sequential access of data transfer to said storage device, wherein said estimating means adopts the residual bytes of sequential access as said index.

2. A storage controller according to claim 1, wherein said bus load estimating means includes means for estimating bus load characteristics based on an amount of data transfer during sequential access to said storage device.

3. A storage controller according to claim 1, wherein said bus mode selecting means selects one of a sequential mode for emphasizing data transfer throughput and a random mode for emphasizing control information transfer throughput as said one bus mode.

4. A storage controller according to claim 1, wherein said bus mode selecting means selects the bus mode based on whether said residual bytes are increasing or decreasing.

5. A storage controller according to claim 1, wherein each of said buses is used for any one of three uses consisting of control data transfer, data transfer, and control data and data transfer, and wherein said bus mode selecting means selects for each said bus a predetermined bus use assignment pattern made of the three bus uses as said one bus mode.

6. A storage controller according to claim 3, wherein said bus load estimating means includes bus load measuring means for measuring and providing an actual bus load measurement on each of said buses and determination means for determining whether the bus loads are equally balanced among said buses on the basis of said actual bus load measurement.

7. A storage controller according to claim 6, wherein said bus mode selecting means makes a selection when said determination means has determined the bus loads are not balanced.

8. A storage controller according to claim 7, wherein said bus mode selecting means selects a bus mode which reduces dispersion of the bus loads among said buses.

9. A storage controller connected between a processor and a storage device for controlling data transfer therebetween, comprising:

a storage device adapter for controlling said storage device;

a cache memory for storing part of the data held in said storage device;

a channel adapter for communicating with said processor and for processing input/output requests received from said processor;

a control memory for storing control information used for communication between said storage device adapter and said channel adapter;

a plurality of buses each connected to at least two of said storage device adapter, said cache memory, said channel adapter and said control memory to transfer data and control information;

bus load estimating means for obtaining an index for bus load characteristics indicating a proportion of data transfer and control information transfer on said plurality of buses;

bus mode selecting means for selecting one of a plurality of a bus mode that determines utilization of said buses based on the index obtained by said bus load estimating means; and

each of said storage device adapter having bus access means and said channel adapter, for accessing said buses in accordance with the bus mode selected by said bus mode selecting means,

wherein each of said buses is used for one of two uses consisting of control data transfer and data transfer, and wherein said bus mode selecting means selects for each said bus a predetermined bus use assignment pattern made of the two bus uses as said one bus mode.

10. A storage controller connected between a processor and a storage device for controlling data transfer therebetween, comprising:

a storage device adapter for controlling said storage device;

a cache memory for storing part of the data held in said storage device;

a channel adapter for communicating with said processor and for processing input/output requests received from said processor;

a control memory for storing control information used for communication between said storage device adapter and said channel adapter;

a plurality of buses each connected to at least two of said storage device adapter, said cache memory, said channel adapter and said control memory to transfer data and control information;

bus load estimating means for obtaining an index for bus load characteristics indicating a proportion of data transfer and control information transfer on said plurality of buses;

bus mode selecting means for selecting one of a plurality of a bus mode that determines utilization of said buses based on the index obtained by said bus load estimating means; and

each of said storage device adapter having bus access means and said channel adapter, for accessing said buses in accordance with the bus mode selected by said bus mode selecting means,

wherein said plurality of buses being three buses used for any one of three uses consisting of control data transfer, data transfer, and control data and data transfer;

said bus mode selecting means selecting for each said bus a predetermined bus use assignment pattern made of the three bus uses as said one bus mode during normal operation, and in the event of a failure of one of said three buses, assigning one of the other two buses to control data transfer and the other of the two other buses to data transfer, and in the event of a failure of two of said three buses, assigning the remaining one of said three buses to control data and data transfer.

11. A bus control method for a storage controller connected between a central processing unit and a storage unit and comprising a plurality of modules and a plurality of buses transferring data and control information between the modules, said method comprising the steps of:

obtaining, by one of the modules, bus load characteristics representing a proportion of data transfer and control information transfer on said plurality of buses;

selecting, by said one module, one of a plurality of bus modes that determines bus utilization based on the bus load characteristics;

communicating the selected bus mode selected in said selecting step from said one of the modules to the other of said modules; and

accessing, by each of said modules, said buses in accordance with said selected bus mode;

wherein said selecting step includes a step of allocating at least one of data transfer and control information transfer to each of said buses according to said selected bus mode.

13. A bus control method according to claim 11, further comprising a step of determining whether said bus loads of said buses are balanced among said buses, and wherein said selecting step is executed when the bus loads are not balanced as a result of said determining.

12. A bus control method for a storage controller connected between a central processing unit and a storage unit and comprising a plurality of modules and a plurality of buses transferring data and control information between the modules, said method comprising the steps of:

obtaining, by one of the modules, bus load characteristics representing a proportion of data transfer and control information transfer on said plurality of buses;

selecting, by said one module, one of a plurality of bus modes that determines bus utilization based on the bus load characteristics;

communicating the selected bus mode selected in said selecting step from said one of the modules to the other of said modules; and

accessing, by each of said modules, said buses in accordance with said selected bus mode

wherein said obtaining step includes the steps of measuring bus loads of said buses, and detecting residual byte of sequential access of data transfer to said storage unit and wherein said selecting step selects the one bus mode in accordance with said bus loads and said residual bytes.