Semiconductor device containing conductor plug that can reduce contact resistance

• US 5,641,991 A
• Filed: 08/31/1995
• Issued: 06/24/1997
• Est. Priority Date: 09/01/1994
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sakoh, Takashi
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): ARROYO, TERESA M
• Application Number:
  US08/521,737
• Time in Patent Office: 663 Days
• Field of Search: 257/752, 257/754, 257/755, 257/382, 257/384, 257/385, 257/903
• US Class Current: 257/755
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A lower-level conductor layer is formed in a surface of, on or over a semiconductor substrate. An interlayer insulator film is formed on the lower-level conductor layer. An upper-level conductor layer such as an interconnection layer of the semiconductor device is formed on the interlayer insulator film. A conductor plug is formed in a contact hole of the interlayer insulator film. The lower-level conductor layer and the upper-level conductor layer are electrically connected with each other through the conductor plug. A top part of the conductor plug protrudes from the interlayer insulator film. The upper-level conductor layer is contacted with a top face and a side face of the top part of the conductor plug. Both the contact resistance between the conductor contact and the upper-level conductor layer and the resistance of the upper-level conductor layer itself can be reduced without using a special equipment and a special process.

Claims

1. A semiconductor device, comprising:

a) a lower-level conductor layer formed in a semiconductor substrate;

b) an interlayer insulator film, formed to cover the lower-level conductor layer, and having a penetrating hole;

c) an upper-level conductor layer formed on the interlayer film, the upper-level conductor layer having a multilayer structure including;

c2) a silicon sublayer; and

c1) a metal silicide sublayer which contacts the silicon sublayer; and

d) a conductor plug which is formed in the hole of the interlayer film and which electrically connects the lower-level conductor layer and the upper-level conductor layer, the conductor plug including;

d1) a top part protruding from the silicon sublayer of the upper-level conductor layer, the top part having a top face and a side face which contact the metal silicide sublayer of the upper-level conductor layer to reduce contact resistance between the conductor plug and the upper-level conductor layer.

2. The device of claim 1, wherein:

the conductor plug is made of polysilicon.

3. The device of claim 1, wherein:

the silicon sublayer of the upper-level conductor layer includes polysilicon doped with an impurity at a doping concentration less than 1×

10²⁰ atoms/cm³.

4. The device of claim 1, wherein:

the interlayer insulator film has a multilayer structure including a top layer of non-doped SiO₂.

5. The device of claim 1, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes TiSi₂.

6. The device of claim 1, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes WSi₂.

7. The device of claim 1, wherein the interlayer insulator film includes:

a lower sublayer including SiO₂ ;

a second sublayer including BPSG; and

an upper sublayer including SiO₂ having no impurity doping.

8. The device of claim 1, wherein the interlayer insulator film includes:

a lower sublayer including SiO₂ ; and

an upper sublayer including BPSG.

9. The device of claim 8, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes TiSi₂.

10. The device of claim 8, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes WSi₂.

11. A semiconductor device, comprising:

a) a lower-level conductor layer formed in a semiconductor substrate;

b) an interlayer insulator film formed to cover the lower-level conductor layer, the interlayer insulator film having a first hole;

c) an upper-level conductor layer formed on the interlayer insulator film and having a two-layer structure including;

c1) a silicon sublayer formed on the interlayer insulator film and having a second hole positioned over the first hole; and

c2) a metal silicide sublayer formed on the silicon sublayer; and

d) a conductor plug, electrically connecting the lower-level conductor layer and the upper-level conductor layer, and formed to extend vertically within the first hole and the second hole, the conductor plug including;

d1) a bottom end which contacts the lower-level conductor layer; and

d2) a top part of the conductor plug, protruding from the silicon sublayer through the second hole and having a top face and a side face which are covered by the metal silicide sublayer to reduce contact resistance between the conductor plug and the upper-level conductor layer.

12. The device of claim 11, wherein:

the silicon sublayer of the upper-level conductor layer includes polysilicon doped with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³.

13. The device of claim 11, wherein:

the interlayer insulator film has a multilayer structure including a top layer of non-doped SiO₂.

14. The device of claim 11, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes TiSi₂.

15. The device of claim 11, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes WSi₂.

16. The device of claim 11, wherein the interlayer insulator film includes:

a lower sublayer including SiO₂ ;

a second sublayer including BPSG; and

an upper sublayer including SiO₂ having no impurity doping.

17. The device of claim 11, wherein the interlayer insulator film includes:

a lower sublayer including SiO₂ ; and

an upper sublayer including BPSG.

18. The device of claim 17, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes TiSi₂.

19. The device of claim 17, wherein, in the upper-level conductor layer:

the silicon sublayer includes a patterned polysilicon layer with an impurity at a doping concentration of less than 1×

10²⁰ atoms/cm³ ; and

the metal silicide sublayer includes WSi₂.