Short circuit current free dynamic logic clock timing

• US 5,642,061 A
• Filed: 04/17/1995
• Issued: 06/24/1997
• Est. Priority Date: 04/17/1995
• Status: Expired due to Fees

• Current Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Inventors: Gorny, Douglas J.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/423,540
• Time in Patent Office: 799 Days
• Field of Search: 326/95, 326/97-98
• US Class Current: 326/97
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

An apparatus and method for providing short circuit current free dynamic logic building blocks comprising P-logic and N-logic dynamic domino building blocks having separate clocks for driving the P-logic and N-logic evaluate and pre-charge stages. The P-logic building gates are pre-charged to a zero volt output and upon the transition from high to low on the input line, will provide a high output during the evaluation cycle. Conversely, the N-logic building blocks are pre-charged with a high output level and upon the transition of a low to high input to the building block device, will provide a low output signal during the evaluation period. Both building block types are pre-charged again at the end of the evaluation period to provide an inherently glitch-free dynamic logic device. Separate evaluate and charge clock signals are provided to each of the P-logic and N-logic building blocks which are configured to provide a non-overlapping charge and evaluation cycle. The active portions of the pre-charge, evaluate cycles, and the transitions between are made mutually exclusive. A static latch is provided for use in DC operations upon shut off of the charge clock. In an alternative embodiment, a dynamic latch is provided for use in a minimal frequency clocking embodiment of the dynamic building blocks where charge cycles are sufficiently frequent to compensate for charge decay.

Claims

1. A short circuit current and glitch free logic building block comprising:

a NP domino logic building block having an input and an output, said input receiving a first input signal in a first input state;

a clock circuit for generating a charge clock signal and an evaluation clock signal, said charge clock signal being asserted during a charge cycle of said block for pre-charging said NP domino logic building block output to a first output state, said evaluation clock signal being asserted during an evaluation cycle of said block for evaluating said first input signal on said input and for driving said NP domino logic building block output to a second output state upon the transition of said first input signal from said first input state to a second input state during said evaluation cycle, said clock circuit being configured such that neither said charge clock signal nor said evaluation clock signal are asserted simultaneously; and

a short circuit current free latch for conditioning said first input signal prior to input to said NP domino logic building block, said latch comprising an input port for receiving said first input signal, an intermediate node for storing an intermediate signal value portion of said first input signal and an output port for coupling said intermediate signal value to said NP domino logic building block, said latch holding said intermediate signal value of said first input signal at a steady state over said evaluation cycle and said charge cycle of said block by latching and delaying said first input signal at said intermediate node until the next evaluation cycle of said building block.

2. The apparatus of claim 1, further including a short circuit current free keeper circuit for maintaining said intermediate value signal portion in said intermediate node until a next evaluation cycle is asserted in said building block.

3. The apparatus of claim 2, wherein said keeper circuit includes a low value detector, a high value detector, low value maintenance circuitry and high value maintenance circuitry, said low and high value detectors being coupled to said intermediate node for detecting said intermediate value signal portion during said evaluation cycle of said building block, said keeper circuit being responsive to said charge clock signal such that during said building block charge cycle, said keeper circuit low and high value maintenance circuitry refresh said intermediate value signal portion on said intermediate node prior to decay of said intermediate signal portion.

4. A cascaded domino logic circuit comprising:

at least one N-logic building block having a first input receiving a first input signal in a first input state and a first output;

at least one P-logic building block having a second input receiving a second input signal in a second input state and a second output;

said at least one N-logic building block and said at least one P-logic building block being connected output-to-input in linear unbranched cascade fashion with an N-logic building block alternating with a P-logic building block in said cascade;

a clock circuit generating an N-logic block charge clock signal and separate N-logic block evaluation clock signal, and a P-logic block charge clock signal and separate P-logic block evaluation clock signal;

said N-logic charge clock signal being asserted during a charge cycle of said N domino logic building block for pre-charging said N domino logic building block output to a first output state, said N-logic evaluation clock signal being asserted during an N-logic block evaluation cycle of said N domino logic building block for evaluating said first input signal on said input and for driving said N domino logic building block output to a third output state upon the transition of said first input signal from said first input state to a third input state during said N-logic block evaluation cycle, said clock circuit being configured such that neither said N-logic block charge clock signal nor said N-logic block evaluation clock signal are asserted nor in transition simultaneously thereby providing separate non-overlapping and non-intersecting N-logic block precharge and evaluation cycles;

said P-logic charge clock signal being asserted during a charge cycle of said N domino logic building block for pre-charging said N domino logic building block output to a first output state, said P-logic evaluation clock signal being asserted during an P-logic block evaluation cycle of said N domino logic building block for evaluating said second input signal on said input and for driving said N domino logic building block output to a fourth output state upon the transition of said second input signal from said second input state to a fourth input state during said P-logic block evaluation cycle, said clock circuit being configured such that neither said P-logic block charge clock signal nor said P-logic block evaluation clock signal are asserted nor in transition simultaneously thereby providing separate non-overlapping and non-intersecting P-logic block pre-charge and evaluation cycles.

5. The apparatus of claim 4, wherein said at least one N-logic building block comprises a plurality of N-logic building blocks.

6. The apparatus of claim 5, wherein said at least one P-logic building block comprises a plurality of P-logic building blocks.

7. The apparatus of claim 4, further comprising a short circuit current free latch for conditioning said first input signal prior to input to one of said N-logic or P-logic domino logic building block, said latch comprising an input port for receiving said an input signal, an intermediate node for storing an intermediate signal value portion of said input signal and an output port for coupling said intermediate signal value to said domino logic building block, said latch holding said intermediate signal value of said input signal at a steady state over an evaluation cycle for said logic block and said charge cycle of said block by latching and delaying said input signal at said intermediate node until the next evaluation cycle of said logic building block.

8. The apparatus of claim 7, further including a short circuit current free keeper circuit for maintaining said intermediate value signal portion in said intermediate node until a next evaluation cycle is asserted in said building block.

9. The apparatus of claim 8, wherein said keeper circuit includes a low value detector, a high value detector, low value maintenance circuitry and high value maintenance circuitry, said low and high value detectors being coupled to said intermediate node for detecting said intermediate value signal portion during said evaluation cycle of said building block, said keeper circuit being responsive to said charge clock signal such that during said building block charge cycle, said keeper circuit low and high value maintenance circuitry refresh said intermediate value signal portion on said intermediate node prior to decay of said intermediate signal portion.

10. The apparatus of claim 4, wherein said logic blocks are cascaded without intervening static inverters between each of said blocks.