Sampled data automatic gain control

• US 5,642,075 A
• Filed: 12/21/1995
• Issued: 06/24/1997
• Est. Priority Date: 12/21/1995
• Status: Expired due to Term

• Current Assignee: Exelis Incorporated (L3Harris Technologies, Inc.)
• Original Assignee: ITT Corporation (ITT, Inc.)
• Inventors: Bell, Andrew G.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US08/576,582
• Time in Patent Office: 551 Days
• Field of Search: 330/129, 330/133, 330/136, 330/140, 330/278, 330/279, 330/280
• US Class Current: 330/129
• CPC Class Codes: H03G 3/3026 the gain being discontinuously variable, e.g. controlled by switching

Abstract

An amplifier circuit employing automatic gain control (AGC), with the gain responsive to a varying input signal level, and particularly adapted for manufacture as an integrated circuit. In a preferred embodiment, an error voltage is produced which is indicative of the difference between the RMS output voltage of the amplifier and a target RMS voltage. A ramp generator generates a ramp voltage in accordance with a digital count generated by a ripple counter. A comparator then produces a control signal in accordance with the difference between the ramp voltage and the error voltage. When the control signal is indicative of the amplifier output voltage differing from the target voltage, the gain is updated in accordance with the digital count and the count and ramp voltage are reset.

Claims

1. Apparatus for automatically controlling the gain of an amplifier having an input terminal for receiving an input signal of varying amplitude, an output terminal for providing an output voltage, and a control terminal for receiving a control voltage operable to control said gain, said apparatus comprising:

means for providing an error voltage indicative of a difference between said output voltage of said amplifier and a desired target voltage;

counting means, coupled to said amplifier control terminal, for generating digital words;

means for generating a plurality of voltage levels within a predetermined time interval with each said voltage level indicative of an associated digital word;

comparison means for comparing said plurality of voltage levels with said error voltage and for providing a control signal when said error voltage is within a predetermined range of any of said voltage levels; and

means responsive to said control signal for providing said control voltage to said amplifier in accordance with said digital word whereby said gain is updated, and wherein said means responsive to said control signal is operable to terminate said counting and said generating of said voltage levels.

2. The apparatus according to claim 1 wherein said means for generating a plurality of voltage levels comprises a ramp generator for generating a linear ramp voltage that ramps from a minimum voltage to a predetermined maximum voltage as said digital words are incremented from a minimum count to a maximum count within said predetermined time interval.

3. The apparatus according to claim 2 wherein said gain is controlled to generate said output voltage substantially equal to a target root mean squared (RMS) output signal level, designated "Vtarget", and further comprising a peak detector to detect a peak level of said amplifier output voltage, said peak voltage being compared with a reference voltage to produce said error voltage.

4. The apparatus according to claim 3 wherein said error voltage is provided by a subtracter coupled to said peak detector and to said comparison means, said subtracter having first and second inputs, said peak level being applied to said first input, and said reference voltage of a value equal to 2×

2⁰⁵ ×

Vtarget is applied to said second input, said subtracter subtracting said peak level from said reference voltage to provide said error voltage.

5. The apparatus according to claim 2 wherein said means responsive to said control signal is operable to reset the digital count to said minimum count and to reset said ramp voltage to said minimum voltage, whenever said control signal is provided.

6. The apparatus according to claim 2 wherein,

in the absence of said control signal, said gain is updated to a maximum gain whenever said maximum count is reached.

7. The apparatus according to claim 2 wherein said means responsive to said control signal comprises:

a gain latch, coupled to said counting means, for receiving said digital words;

a multiplying digital to analog converter (MDAC), coupled to said amplifier and to said gain latch, said MDAC providing an analog control voltage to said amplifier in accordance with said digital words, said analog control voltage controlling circuit parameters of said amplifier and thereby controlling said gain.

8. The apparatus according to claim 7 wherein said means responsive to said control signal further comprises:

a reset control circuit, coupled to said comparison means, said ramp generator, said counting means and said gain latch, said reset control circuit providing a plurality of reset signals responsive to said control signal, said reset signals enabling transfer of a then present digital word on output lines of said counting means to output lines of said gain latch and enabling said counting means to reset said count to said minimum count and said ramp generator to reset said ramp voltage to said minimum voltage.

9. The apparatus according to claim 8 wherein said reset control circuit provides said reset signals responsive to said counting means reaching said maximum count, thereby enabling said maximum count to be transferred to said output lines of said gain latch.

10. The apparatus according to claim 1 wherein said apparatus is fabricated as an integrated circuit.

11. The apparatus according to claim 8 wherein,

said counting means comprises an asynchronous counter having a first plurality of D latch flip flops each having a Q output line wherein said digital words are provided;

and

said gain latch comprises a second plurality of D latch flip flops each having a D input line for receiving said digital words from said first plurality of D latch flip flops, and each having a clock input line for receiving one of said reset signals from said reset control circuit to enable transfer of said digital words to Q output lines of said second plurality of D latch flip flops.

12. The apparatus according to claim 8 wherein said ramp generator comprises:

an operational amplifier having an output terminal wherein said ramp voltage is provided, a feedback loop including a first capacitor and a switch responsive to one of said reset control signals to reset said ramp voltage to zero volts;

a second capacitor coupled to an input terminal of said operational amplifier; and

,

means for varying voltage stored by said first capacitor as a function of time, thereby enabling said ramp voltage to be produced.

13. The apparatus according to claim 12 further comprising:

clock generating means for providing clock pulses to said counting means and to said ramp generator to synchronize said digital count with said ramp voltage; and

,

switch means, coupled to said second capacitor, for receiving said clock pulses to enable said voltage stored by said second capacitor to be varied as a function of time.

14. The apparatus according to claim 4 wherein said ramp generating means is adapted to ramp said ramp voltage from zero volts to one half of said reference voltage as said digital count is incremented from a minimum count to a maximum count within a predetermined time interval;

and,

wherein said comparison means comprises a comparator having inverting and noninverting input terminals and an output terminal, said ramp voltage being applied to said noninverting input terminal, said error voltage being applied to said inverting input terminal, said comparator providing said control signal on said output terminal as a given logic level when said ramp voltage exceeds said error voltage.

15. The apparatus according to claim 3 further comprising:

a sample and hold circuit coupled to said amplifier output for providing an output voltage sample;

a low pass filter coupled to said sample and hold circuit for low pass filtering of said output voltage sample;

a rectifier having an input coupled to said low pass filter and an output coupled to said peak detector for providing a rectified output voltage sample to said peak detector.

16. Apparatus for amplifying an input signal of varying amplitude to produce an output signal, comprising:

range control means for providing a digital control word indicative of an amplitude range that said input signal is within;

preamplification means, coupled to said range control means, for amplifying said input signal at a gain corresponding to said digital control word to produce an intermediate amplified signal;

an output amplifier having an input terminal for receiving said intermediate amplified signal, an output terminal for providing said output signal, and a control terminal for receiving a control voltage operable to control said gain;

means for providing an error voltage indicative of a difference between said output signal and a desired target voltage;

counting means for generating digital words;

means for generating a plurality of voltage levels within a predetermined time interval with each said voltage level indicative of an associated digital word;

comparison means for comparing said plurality of voltage levels with said error voltage and for providing a control signal when said error voltage is within a predetermined range of any of said voltage levels; and

means responsive to said control signal for providing said control voltage to said amplifier in accordance with said digital word whereby said gain is updated to provide said output signal at a substantially constant RMS amplitude, and wherein said means responsive to said control signal is operable to terminate said counting and said generating of said voltage levels.

17. The apparatus according to claim 16 wherein said range control means comprises:

a peak detector for providing a peak signal indicative of the peak level of said input signal;

an analog to digital (A/D) converter coupled to said peak detector and to said preamplification means, for converting said peak signal into said digital control word, said digital control word being of a predetermined number of bits, with each word corresponding to a given amplitude range of said input signal.

18. The apparatus according to claim 16 wherein said apparatus is fabricated as an integrated circuit.

19. Method for automatically controlling gain of an amplifier producing an output signal in response to a varying input signal level to said amplifier, comprising the steps of:

providing an error voltage indicative of a difference between said output signal of said amplifier and a desired target voltage;

generating a digital count;

generating a plurality of voltage levels according to said digital count;

providing a control signal in accordance with the difference between said voltage levels and said error voltage; and

updating the gain of said amplifier, responsive to said control signal, to a value corresponding to said digital count.

20. The method according to claim 19 further comprising the steps of:

providing a digital control word indicative of an amplitude range that said input signal is within; and

preamplifying said input signal at a gain corresponding to said digital control word.