Circuit arrangement for controlling the display of a cursor symbol of variable magnitude and shape in a cursor field of variable magnitude

• US 5,642,132 A
• Filed: 01/10/1995
• Issued: 06/24/1997
• Est. Priority Date: 05/10/1993
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Buhr, Wolfgang
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): BELL, PAUL A
• Application Number:
  US08/362,606
• Time in Patent Office: 896 Days
• Field of Search: 345/145, 345/157, 345/159, 345/162
• US Class Current: 345/157
• CPC Class Codes: G09G 5/08 Cursor circuits

Abstract

A circuit arrangement for the display of a cursor symbol of variable magnitude addresses the cursor memory by means of a separate addressing device which operates only during display of the cursor field. The organization of the memory for the cursor symbol, constructed as a matrix memory, is fully independent of the rows and columns of the cursor field, i.e. to the cursor symbol the memory appears as a pure linear memory. As a result, this memory can be utilized in a substantially improved manner and the display of even large cursor symbols requires only a limited storage capacity.

Claims

1. A display device, comprising:

image generating means for generating an image in a raster scan format of pixels, said image generating means comprising cursor generating means for cursor generating and mixing means fed by said cursor generating means for mixing said cursor into said raster scan format for displaying, said cursor generating means comprising

input means for receiving recurrent scanning control signals comprising a pixel clock signal,

indicator means for indicating the position of a cursor field in the image,

clip means fed by said input means and by said indicator means for generating a binary cursor window signal,

a cursor memory having a plurality of locations each for storing a data word, all stored data words indicating at least one cursor pattern,

addressing means fed by said input means and by said clip means for under control of a first value of said binary cursor window signal accessing successive locations for outputting data words, thereby advancing to each next location after a number of pixel clock signals which corresponds to the number of bits of each data word divided by a first number of bits used for the display of each cursor pixel,

parallel-serial converter means for receiving each data word output by said memory and for supplying the first number of different consecutive bits of the received data word at each pixel clock signal which occurs during the first value of said binary cursor window signal,

switch means controlled by said binary cursor window signal and fed by the parallel-serial converter for controlling the data supplied to a display device.

2. A circuit arrangement for controlling a cursor display in a raster scan image, said arrangement comprising:

input means for receiving recurrent scanning control signals comprising a pixel clock signal,

indicator means for indicating the position of a cursor field in the image,

clip means fed by said input means and by said indicator means for generating a bivalent cursor window signal,

a cursor memory having a plurality of locations each for storing a data word, all stored data words indicating at least one cursor pattern,

addressing means fed by said input means and by said clip means for under control of a first value of said binary cursor window signal accessing successive locations for outputting data words, thereby advancing to each next location after a number of pixel clock signals which corresponds to the number of bits of each data word divided by a first number of bits used for the display of each cursor pixel,

parallel-serial converter means for receiving each data word output by said memory and for supplying the first number of different consecutive bits of the received data word at each pixel clock signal which occurs during the first value of said binary cursor window signal,

switch means controlled by said clipping signal and fed by the parallel-serial converter for controlling the data supplied to a display device.

3. A circuit arrangement as claimed in claim 2, characterized in that the addressing means is advanced to the next location in response to a new raster line.

4. A circuit arrangement as claimed in claim 2 wherein said indicator means comprises:

first registers for storing position data determining the position of the cursor in the image,

a second register for storing the number of lines of the cursor,

a third register for storing the number of pixels per line of the cursor,

a first counter for counting a number of lines which corresponds to the contents of the second register, and

a second counter for repeated counting of a number of pixels corresponding to the contents of the register for each new line,

the first registers comprising a first sub-register for storing the position of the cursor in the horizontal direction in the image and a second sub-register for storing the position of the cursor in the vertical direction in the image,

a comparator which generates a first start signal when the horizontal control signals equal the contents of the first sub-register in order to set the first counter to a position corresponding to the contents of the second register and, subsequently, to make the first counter count at a pixel frequency until it reaches an initial position and to make it output a horizontal window signal for the duration of the counting, said comparator generating a second start signal when the vertical control signals equal the contents of the second sub-register in order to set the second counter to a position corresponding to the contents of the third register and, subsequently, to make the second counter count at a line frequency until it reaches an initial position and to make it output a vertical window signal for the duration of counting, the combination of the two window signals determining the binary cursor window signal.

5. A circuit arrangement as claimed in claim 4, further comprising:

a switch which applies the data output by the parallel- serial-converter to a display device;

a logic element for generating said binary cursor window signal from the two window signals serving to control said switch.

6. A circuit arrangement as claimed in claim 4, further comprising:

a switch which applies the data output by the parallel-serial converter to a display device;

the second counter serves to count the pixels only during the counting by the first counter and generates during counting said binary cursor window signal serving to control said switch.