Electro-optical device

• US 5,642,213 A
• Filed: 05/20/1994
• Issued: 06/24/1997
• Est. Priority Date: 03/15/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hiroki, Masaaki, Mase, Akira
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Dudek, James A.
• Application Number:
  US08/247,924
• Time in Patent Office: 1,131 Days
• Field of Search: 359/54, 359/58, 359/59, 359/57, 359/87, 340/784, 257/59, 257/66, 257/72, 257/353, 257/351, 148/DIG. 141, 437/170, 437/101, 437/983, 437/41, 437/43, 437/42, 205/124, 205/125, 205/78
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.

Claims

1. A semiconductor device comprising:

a semiconductor island formed on an insulating surface;

a first thin film transistor formed with said semiconductor island, said first thin film transistor comprising a first channel region formed in said semiconductor island, a pair of first impurity regions formed in said semiconductor island with said first channel region interposed therebetween, first offset regions between said first channel region and said first impurity regions, and a first gate electrode formed over said first channel region; and

a second thin film transistor formed with said semiconductor island and electrically connected to said first thin film transistor, said second thin film transistor comprising a second channel region formed in said semiconductor island, a pair of second impurity regions formed in said semiconductor island with said second channel region interposed therebetween, second offset regions between said second channel region and said second impurity regions, and a second gate electrode formed over said second channel region, said second gate electrode being connected to said first gate electrode;

wherein one of said first impurity region of said first transistor and adjacent one of said second impurity regions have a same conductivity type and are electrically connected with one another, and

wherein each gate electrode of said first and second thin film transistors comprises a metal and has a surface thereof covered with an oxide layer which is formed by oxidizing a surface of said gate electrode.

2. The device of claim 1 wherein said metal of the gate electrode is selected from the group consisting of aluminum, molybdenum and chromium.

10. A device as in claim 1, 3, 6 or 8 wherein said electrically connected first and second impurity regions at least partially overlap.

11. A device as in claims 1, 3, 6 or 8 wherein said electrically connected first and second impurity regions are contiguous with one another.

3. A semiconductor device comprising:

a semiconductor island formed on an insulating surface;

a first thin film transistor formed with said semiconductor island, said first thin film transistor comprising a first channel region formed in said semiconductor island, a pair of first impurity regions formed in said semiconductor island with said first channel region interposed therebetween, first offset regions between said first channel region and said first impurity regions, and a first gate electrode formed over said first channel region, said first gate electrode comprising a metal and covered with an oxide layer of said first gate electrode;

a second thin film transistor formed with said semiconductor island and electrically connected to said first thin film transistor, said second thin film transistor comprising a second channel region formed in said semiconductor island, a pair of second impurity regions formed in said semiconductor island with said second channel region interposed therebetween, second offset regions between said second channel region and said second impurity regions, and a second gate electrode formed over said second channel region, said second gate electrode comprising a metal and covered with an oxide layer of said second gate electrode, wherein one of said second impurity regions has a same conductivity type as and is electrically connected to an adjacent one of said first impurity regions of the first transistor;

an interlayer insulator formed on said first and second thin film transistors; and

a wiring formed on said interlayer insulator,

wherein said wiring is electrically connected to another one of said first impurity regions of said first thin film transistor through a contact hole formed in said interlayer insulator, and

wherein any one of said impurity regions located between the channel regions is not connected to any electrode or lead.

4. The device of claim 3 wherein said metal of each of said first and second gate electrodes is selected from the group consisting of aluminum, molybdenum and chromium.

5. The device of claim 3 wherein said wiring is electrically isolated from said adjacent one of said first impurity regions.

6. A semiconductor device comprising:

a semiconductor island formed over a substrate;

a plurality of gate electrodes adjacent to said island, said gate electrodes being electrically connected with one another;

a gate insulating layer interposed between said gate electrodes and said semiconductor island;

a plurality of channel regions formed in said semiconductor island adjacent to said gate electrodes;

a plurality of impurity regions formed in said semiconductor island and contiguous to said channel regions, said impurity regions having a same impurity conductivity type with one another and

offset regions formed between said channel regions and said impurity regions,

wherein said gate electrodes comprise an oxidizable material and are provided with an oxide layer of said material on a surface thereof.

7. The semiconductor device of claim 6 wherein said anodizable material of said gate electrodes is selected from the group consisting of aluminum, molybdenum and chromium.

8. A semiconductor device comprising:

a semiconductor island formed over a substrate;

a plurality of gate electrodes formed over said island, said gate electrodes being electrically connected with one another;

a gate insulating layer interposed between said gate electrodes and said semiconductor island;

a plurality of channel regions formed in said semiconductor island below said gate electrodes; and

a plurality of impurity regions formed in said semiconductor island and contiguous to said channel regions, said impurity regions having a same impurity conductivity type with one another,

an interlayer insulator formed on said semiconductor island;

a wiring formed on said interlayer insulator and electrically connected to one of grid impurity regions,

wherein said gate electrode comprises an oxidizable material and is provided with an oxide layer of said material on a surface thereof, and

wherein said impurity regions are formed in a self-aligned manner with respect to said gate electrodes having said oxide layer thereon.

9. The semiconductor device of claim 8 wherein said anodizable material of said gate electrodes is selected from the group consisting of aluminum, molybdenum and chromium.

12. A semiconductor device comprising:

a semiconductor island formed on an insulating surface;

a plurality of channel legions formed in said semiconductor island, pairs of impurity regions formed in said semiconductor island with said plurality of channel regions respectively interposed therebetween, and a plurality of gate electrodes respectively formed over said channel regions, said gate electrodes each comprising a metal and being covered with an oxide layer of the associated gate electrode and being connected to each other;

wherein on impurity region of each said pair of impurity regions has a same conductivity type as and is electrically connected to one of the impurity regions of an adjacent pair of impurity regions, and

wherein said pairs of impurity regions are formed in a self-alignment manner with respect to said gate electrodes having said oxide layer formed thereon.

13. The device of claim 12 wherein said electrically connected impurity regions are contiguous with one another.

14. The device of claim 12 wherein said electrically connected impurity regions at least partially overlap.

15. A semiconductor device comprising:

a semiconductor island formed on an insulating surface;

a plurality of channel regions formed in said semiconductor island, pairs of impurity regions formed in said semiconductor island with said plurality of channel regions respectively interposed therebetween, an offset region interposed between said channel regions and said impurity regions and a plurality of gate electrodes respectively adjacent said channel regions, said gate electrodes each comprising a metal and being covered with an oxide layer of the associated gate electrode and being connected with each other;

wherein one impurity region of each said pair of impurity regions has a same conductivity type as and is electrically connected to one of the impurity regions of an adjacent pair of impurity regions.

16. The device of claim 15 wherein said electrically connected impurity regions are contiguous with one another.

17. The device of claim 15 wherein said electrically connected impurity regions at least partially overlap.

18. The device of claim 15 including a plurality of gate insulating layers respectively interposed between said gate electrodes and said channel regions.