Flash EEPROM system cell array with more than two storage states per memory cell

• US 5,642,312 A
• Filed: 05/22/1996
• Issued: 06/24/1997
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/650,116
• Time in Patent Office: 398 Days
• Field of Search: 365/185.01, 365/185.18, 365/185.19, 365/185.24, 365/185.28, 365/185.29, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. For an array of electrically alterable memory cells divided into blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, said memory cells individually including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating the array, comprising:

establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable programmed states of the individual cells in excess of two,

setting the effective threshold voltage level of at least one addressed cell within one of said blocks from a starting level to one of the plurality of threshold voltage levels by altering the amount of charge on the floating gate of said addressed cell until the effective threshold voltage of said addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, whereby the state of said addressed cell is set to one of said plurality of programmed states, setting the effective threshold voltage level including the steps of;

applying a given voltage to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of the addressed cell from the starting level toward said one of the plurality of threshold voltage levels,

thereafter reading an electrical parameter of the addressed cell to determine whether the effective threshold voltage of the addressed cell has reached said one of the plurality of threshold voltage levels, and

repeating the voltage applying and reading steps until it is detected by the reading step that the effective threshold voltage of the addressed cell has been set to said one of the plurality of threshold voltage levels.

2. The method of claim 1, wherein the voltage applying step includes making said given voltage and said predetermined time such that the effective threshold voltage of the addressed cell is changed by less than one-half a difference between two adjacent of said plurality of effective threshold voltage levels.

3. The method of claim 1 wherein the step of reading includes electrically interrogating the addressed cell and simultaneously comparing a resulting level of an electrical parameter of the addressed cell with a number of reference levels of two or more.

4. The method of claim 1, which additionally comprises, prior to setting the effective threshold voltage level of at least one addressed cell within one of said blocks, of resetting the effective threshold voltage levels of cells within said at least one block to a preset level by the steps of:

applying a given voltage to the cells within said at least one block for a predetermined time sufficient to move the effective threshold voltage level of the cells within said at least one block toward said preset level,

thereafter reading said electrical parameter of the cells within said at least one block to determine whether the effective threshold voltages of the individual cells within said at least one block have reached said preset level, and

repeating the steps of applying voltage and reading the states of the cells within said at least one block until it is detected that the effective threshold voltage of the cells within said at least one block have been reset to said preset level.

5. The method of claim 4 wherein said preset level is made to be substantially equal to one of said plurality of effective threshold voltage levels that correspond to a plurality of detectable programmed states of the individual cells.

6. The method of claim 4 wherein the given voltage applied to the cells within said at least one block during resetting of their effective threshold voltage levels increases when the voltage applying and reading steps are repeated.

7. The method of claim 4 wherein the step of reading said electrical parameter of the cells within said at least one block includes electrically interrogating the cells within said at least one block and simultaneously comparing a resulting level of said electrical parameter of individual ones of the cells within said at least one block with a number of reference levels of two or more.

8. The method of any one of claims 1-7 wherein at least two of said plurality of effective threshold levels result from a net positive charge on the floating gate of the individual cells.

9. The method of any one of claims 1-7 wherein the given threshold level of the individual cells is established to be at least three volts.

10. The method of any one of claims 1-7 wherein the repeating of the voltage applying and reading steps during setting the effective threshold voltage level of said at least one addressed cell is terminated after a preset maximum number of repeats of the voltage applying and reading steps have occurred during setting without setting the effective threshold voltage levels of the addressed cell to said one of the plurality of threshold voltage levels.

11. The method of any one of claims 1-7 wherein the repeating of the voltage applying and reading steps during resetting the effective threshold voltage levels of cells within said at least one block is terminated after a preset maximum number of repeats of the voltage applying and reading steps have occurred during resetting without resetting the effective threshold voltage level of a certain number of the individual cells within said at least one block to said preset level.

12. The method of any one of claims 1-7 which additionally comprises, in response to said at least one addressed cell becoming defective, of substituting therefore a redundant good cell within the array.

13. The method of any one of claims 1-7 which additionally comprises, in response to said at least one block of cells becoming defective, of substituting therefore at least one redundant block of cells within the array.

14. The method of any one of claims 1-7 which additionally comprises accumulating a count of a total number of times that at least one block of cells has been reset.