Static type of semiconductor memory device having great low voltage operation margin
First Claim
1. A static type of semiconductor memory device comprising:
- a power supply line for supplying a power supply voltage;
a static type of memory cell having a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors are provided between output terminals of said flip-flop and said bit lines, respectively, and gates of said transfer MOS transistors are connected to a word line;
a boosting circuit for boosting said power supply voltage;
a word line driving circuit for driving said word line with a boosted voltage supplied from said boosting circuit; and
a voltage control circuit for controlling said boosted voltage to be in the neighborhood of a predetermined voltage such that ratio of current through one of said driving MOS transistors in an on state to current through one of said transfer MOS transistors is set to a desired value.
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Accused Products
Abstract
A static type of semiconductor memory device includes a power supply line for supplying a power supply voltage, a pair of bit lines, a word line, and a memory cell connected to the word line and the pair of bit lines. The power supply voltage is boosted up to provide the boosted voltage on a boosted voltage line. A predetermined voltage is supplied to the word line using the boosted voltage and a write operation or read operation is performed to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line. The predetermined voltage is approximately equal to a sum of the power supply voltage and a threshold voltage of a MOS transistor, resulting in a great low voltage operation margin.
45 Citations
20 Claims
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1. A static type of semiconductor memory device comprising:
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a power supply line for supplying a power supply voltage; a static type of memory cell having a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors are provided between output terminals of said flip-flop and said bit lines, respectively, and gates of said transfer MOS transistors are connected to a word line; a boosting circuit for boosting said power supply voltage; a word line driving circuit for driving said word line with a boosted voltage supplied from said boosting circuit; and a voltage control circuit for controlling said boosted voltage to be in the neighborhood of a predetermined voltage such that ratio of current through one of said driving MOS transistors in an on state to current through one of said transfer MOS transistors is set to a desired value. - View Dependent Claims (5)
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2. A static type of semiconductor memory device comprising:
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a power supply line for supplying a power supply voltage; a static type of memory cell having a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors are provided between output terminals of said flip-flop and bit lines of a pair, respectively, and gates of said transfer MOS transistors are connected to a word line; and voltage adjusting means for adjusting a voltage of said word line to a predetermined voltage such that a ratio of current flowing through one of said two driving MOS transistors in an on state to current flowing through one of said transfer MOS transistors is set to a desired value. - View Dependent Claims (3, 6, 7, 8, 9, 10)
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4. A method of providing a large low voltage operation margin in a static type of semiconductor memory device, comprising the steps of:
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providing in said static type of memory cell a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to a power supply line for supplying a power supply voltage, transfer MOS transistors are provided between output terminals of said flip-flop and bit lines of a pair, respectively, and gates of said transfer MOS transistors are connected to a word line; and adjusting a voltage of said word line to a predetermined voltage such that a ratio of current flowing through one of said two driving MOS transistors in an on state to current flowing through one of said transfer MOS transistors is set to a desired value. - View Dependent Claims (12, 13, 14, 15)
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11. A method of providing a great low voltage operation margin in a static type of semiconductor memory device;
- comprising the steps of;
providing in said static type of memory cell a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors are provided between output terminals of said flip-flop and said bit lines, respectively, and gates of said transfer MOS transistors are connected to a word line; boosting the power supply voltage to provide boosted voltage on a boosted voltage line; adjusting said boosted voltage to generate a predetermined voltage; supplying the predetermined voltage to the word line; and performing a write operation or read operation to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line, wherein the predetermined voltage supplied on the word line is such that ratio of current through one of said driving MOS transistors in an on state to current through one of said transfer MOS transistors is set to a desired value.
- comprising the steps of;
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16. A static type of semiconductor memory device comprising:
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a power supply line for supplying a power supply voltage; a pair of bit lines; a word line; a static type of memory cell having a flip-flop which is composed of two load resistors and two driving MOS transistors respectively connected to said two load resistors, wherein said two load resistors are connected to said power supply line, transfer MOS transistors are provided between output terminals of said flip-flop and said bit lines, respectively, and gates of said transfer MOS transistors are connected to a word line; adjusting means for adjusting a voltage of said word line to a predetermined voltage such that a ratio of current flowing through one of said two driving MOS transistors in an on state to current flowing through one of said transfer MOS transistors is set to a desired value; and an access circuit for performing a write operation or read operation to the memory cell via the pair of bit lines in response to supply of the predetermined voltage to the word line. - View Dependent Claims (17, 18, 19, 20)
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Specification