Fir filters with multiplexed inputs suitable for use in reconfigurable adaptive equalizers

• US 5,642,382 A
• Filed: 03/01/1995
• Issued: 06/24/1997
• Est. Priority Date: 03/01/1995
• Status: Expired due to Fees

• Current Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi America Limited (Hitachi, Ltd.)
• Inventors: Juan, Yujen
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): LUTHER, WILLIAM A
• Application Number:
  US08/396,839
• Time in Patent Office: 846 Days
• Field of Search: 375/229, 375/230, 375/232, 375/233, 375/235, 375/261, 375/266, 375/270, 375/277, 375/321, 375/340, 375/343, 375/346, 375/348, 375/350, 364/724.19, 364/724.03, 364/724.2, 364/572, 329/310, 329/349, 329/350, 329/353, 329/357, 455/109, 455/334, 455/204, 333/28 R, 348/724
• US Class Current: 375/232
• CPC Class Codes: H03H 17/0292 Time multiplexed filters; Time sharing filters
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2218/085 Multipliers
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence

Abstract

Methods and apparatus for providing implementation efficient adaptive equalizers suitable for use with QAM and/or VSB signals are disclosed. Finite impulse response ("FIR") filters are used to implement the disclosed adaptive equalizers. A plurality of arithmetic operator sharing techniques are disclosed for reducing the number of arithmetic operators required to implement the adaptive equalizers. In addition, methods of reconfiguring the arithmetic operators used to implement a QAM equalizer so that they can be used to implement a VSB equalizer circuit are disclosed. Methods of the present invention use multiplexers to reconfigure the FIR filters from a complex decimating FIR filter for use during QAM operation, to a half complex feedforward FIR filter and a real decision feedback FIR filter suitable for use during VSB mode operation of the equalizer circuit of the present invention. Using the methods of the present invention it is possible to implement a 256-tap FIR filter using only 64 sets of arithmetic operators. The adaptive equalizer of the present invention may be used in a demodulator for demodulating QAM and/or VSB signals.

Claims

1. A method of implementing an N tap finite impulse response filter including a series of filter cells, wherein N is an integer greater than one, comprising the steps of:

providing a first filter cell including a first set of arithmetic operators and a first pair of multiplexers for controlling a supply of first tap signals and first tap coefficients to the first set of arithmetic operators; and

operating the first filter cell to calculate tap outputs corresponding to at least a first m taps of the N tap finite impulse response filter and to output the m^th tap output where m is an integer greater than 1 and less than N;

providing a second filter cell including a feedback circuit, a second set of arithmetic operators, and a second pair of multiplexers for controlling a supply of second tap signals and second tap coefficients to the second set of arithmetic operators;

providing a previous filter cell input control multiplexer having a first input coupled to the output of the first filter cell and a second input coupled to the feedback circuit; and

operating the second filter cell to calculate tap outputs corresponding to at least an additional two taps of the N tap finite impulse response filter.

2. The method of claim 1, wherein the tap signals include a tap 1 signal and a tap 2 signal and wherein the tap coefficients include a tap 1 coefficient and a tap 2 coefficient and wherein the step of operating the first filter cell to calculate tap outputs includes the steps of:

operating the first pair of multiplexers to supply the tap 1 coefficient and the tap 1 signal to the first set of arithmetic operators;

operating the first set of arithmetic operators to generate a tap 1 output signal;

operating the first multiplexers to supply the tap 2 coefficient and the tap 2 signal to the first set of arithmetic operators; and

operating the first set of arithmetic operators to generate a tap 2 output signal as a function of the tap 2 coefficient, tap 2 signal, and tap 1 output signal.

3. The method of claim 2, further comprising the steps of:

storing the tap 1 output signal in an accumulator before generating the tap 2 output signal.

4. The method of claim 3, further comprising the steps of:

storing the tap 2 output signal in the accumulator; and

then

storing the tap 2 output signal in a delay element.

5. The method of claim 1, wherein the tap signals and the tap coefficients are complex, and wherein the tap outputs include a real tap output portion and an imaginary tap output portion.

6. A method of sharing arithmetic operators in a feed forward equalizer comprising an N-tap finite impulse response filter for filtering a signal having a first sampling rate, where N is an integer greater than 1, the method comprising the steps of:

providing a first set of multiplexers for receiving real and imaginary portions of a first set of complex tap signals and a second set of multiplexers for receiving real and imaginary portions of a first set of complex tap coefficients;

operating the first and second sets of multiplexers at a rate at least twice the sampling rate, to selectively output the real and the imaginary portions of the first set of complex tap signals and the real and the imaginary portions of the first set of complex tap coefficients;

providing a first set of arithmetic operators; and

operating the first set of arithmetic operators to generate the real portion resulting from a complex multiplication of the real and imaginary portions of the first set of complex tap signals and the real and imaginary portions of the complex tap coefficients output by the first and second sets of multiplexers each time the first and second sets of multiplexers selectively output the real and imaginary portions of the first set of complex tap signals and the real and imaginary portions of the first set of complex tap coefficients.

7. The method of claim 6, further comprising the steps of:

providing a third set of multiplexers for receiving real and imaginary portions of a second set of complex tap signals and a fourth set of multiplexers for receiving real and imaginary portions of a second set of complex tap coefficients;

operating the third and fourth sets of multiplexers at a rate at least twice the sampling rate, to selectively output the real and imaginary portions of the second set of complex tap signals and the real and imaginary portions of the second set of complex tap coefficients;

providing a second set of arithmetic operators;

operating the second set of arithmetic operators to generate a real portion resulting from a complex multiplication of the real and imaginary portions of the second set of complex tap signals and the real and imaginary portions of the second set of complex tap coefficients output by the third and fourth sets of multiplexers each time the third and fourth set of multiplexers output new complex tap signals and tap coefficients.

8. A method of sharing arithmetic operators in a feedback equalizer circuit comprising a real N-tap finite impulse response filter for filtering a signal, where N is an integer greater than 3, the method comprising the steps of:

providing a first multiplexer for receiving a first and second tap coefficient;

providing a second multiplexer for receiving a first and second tap signal;

providing a third multiplexer for receiving a third and forth tap signal;

providing a fourth multiplexer for receiving a third and fourth tap coefficient;

providing a first and second multiplier and a first summer coupled to the first and second multipliers;

operating the first and second multiplexers to output the first tap coefficient and first tap signal, respectively;

operating the third and fourth multiplexers to output the third tap signal and third tap coefficient, respectively;

operating the first and second multipliers to multiply the first tap coefficient with the first tap signal and the third tap coefficient with the third tap signal, to generate first and third tap signal outputs, respectively; and

operating the first summer to sum the first and third tap signal outputs.

9. The method of claim 8, further comprising the steps of:

storing the sum of the first and third tap signal outputs thereby forming a first stored sum;

operating the first and second multiplexers to output the second tap coefficient and second tap signal, respectively;

operating the third and fourth multiplexers to output the fourth tap signal and fourth tap coefficient, respectively;

operating the first and second multipliers to multiply the second coefficient with the second tap signal and the fourth coefficient with the fourth tap signal, to generate second and fourth tap signal outputs, respectively;

operating the first summer to slum the second and fourth tap signal outputs; and

summing the sum of the second and fourth tap signal outputs with the first stored sum to generate the output of the first through fourth taps of the real N-tap finite impulse response filter.

10. The method of claim 9, further comprising the steps of:

providing a fifth multiplexer for receiving a fifth and sixth tap coefficient;

providing a sixth multiplexer for receiving a fifth and sixth tap signal;

providing a seventh multiplexer for receiving a seventh and eighth tap signal;

providing an eighth multiplexer for receiving a seventh and eight tap coefficient;

providing a third and fourth multiplier and a second summer coupled to the first and second multipliers;

operating the fifth and sixth multiplexers to output the fifth tap coefficient and fifth tap signal, respectively;

operating the seventh and eighth multiplexers to output the seventh tap signal and seventh tap coefficient, respectively;

operating the third and fourth multipliers to multiply the fifth tap coefficient with the fifth tap signal and the seventh tap coefficient with the seventh tap signal, to generate fifth and seventh tap signal outputs, respectively; and

operating the second summer to sum the fifth and seventh tap signal outputs.

11. The method of claim 10, further comprising the steps of:

storing the sum of the fifth and seventh tap signal outputs thereby forming a second stored sum;

operating the fifth and sixth multiplexers to output the sixth tap coefficient and sixth tap signal, respectively;

operating the seventh and eight multiplexers to output the eighth tap signal and eighth tap coefficient, respectively;

operating the third and fourth multipliers to multiply the sixth tap coefficient with the sixth tap signal and the eight tap coefficient with the eighth tap signal, to generate sixth and eighth tap signal outputs, respectively;

operating the second summer to sum the sixth and eight tap signal outputs; and

summing the sum of the sixth and eighth tap signal outputs with the second stored sum to generate the output of the fifth through eighth taps of the real N-tap finite impulse response filter.

12. A real 4-tap finite impulse response filter for generating a filter output signal as a function of a first through fourth tap signal and a first through fourth tap coefficient, the 4-tap finite impulse response filter comprising:

a first multiplexer for receiving and selectively outputting a first and a second tap coefficient;

a second multiplexer for receiving and selectively outputting a first and a second tap signal;

a first multiplier coupled to the first and second multiplexers for multiplying the first tap signal with the first tap coefficient and the second tap signal with the second tap coefficient;

a third multiplexer for receiving a third and a fourth tap signal;

a fourth multiplexer for receiving a third and a fourth tap coefficient;

a second multiplier coupled to the third and the fourth multiplexers for multiplying the third tap signals with the third tap coefficient and the fourth tap signal with the fourth tap coefficient; and

a summer coupled to the first and second multiplexers.

13. An N-tap finite impulse response filter circuit for use in a joint VSB/QAM demodulator, wherein N is an integer, the filter circuit comprising:

multiplexer means, including a plurality of multiplexers, for receiving QAM tap signals, VSB tap signals, QAM tap coefficients, VSB tap coefficients, and a modulation type signal, the multiplexer means outputting the received VSB tap signals and the received VSB tap coefficients when the modulation type signal indicates a VSB mode of operation and outputting the received QAM tap signals and the received QAM tap coefficients when the modulation type signal indicates a QAM of mode operation; and

multiplier means coupled to the multiplexer means for multiplying the tap signals and the tap coefficients output by the multiplexer means, the tap coefficients and the tap signals corresponding to the same tap of the N-tap finite impulse response filter circuit being multiplied together.

14. The N-tap finite impulse response filter circuit of claim 13, further comprising:

programmable adder means, coupled to the multiplier means, for receiving the modulation type signal and for summing as a function of the modulation type selection signal the products of the multiplier means.

15. The N-tap finite impulse response filter circuit of claim 14, wherein the multiplexer means and the programmable adder means receive a feed forward/feed back control signal which controls whether the multiplexer means and programmable adder means operate in a feed forward filter mode or a feedback filter mode.