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External defibrillator circuit

  • US 5,643,324 A
  • Filed: 04/10/1995
  • Issued: 07/01/1997
  • Est. Priority Date: 03/15/1993
  • Status: Expired due to Term
First Claim
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1. An external defibrillator high voltage circuit for generating defibrillation pulses, including:

  • a pair of electrodes;

    a charging power source having first and second charge supply terminals;

    first and second output terminals configured for electrical interconnection to the electrodes;

    first and second charge supply terminals configured for electrical interconnection to a charging voltage supply;

    N capacitors Cn where N is at least 2 and n=1 . . . N, for storing electrical energy, each capacitor having first and second terminals, and the first terminal of capacitor C1 electrically coupled to the second charge supply terminal of the charging power source;

    a plurality of diodes, including a diode interconnected between the second terminals of capacitors Cn and Cn+1 for each of the N capacitors;

    a plurality of charging semiconductor switches for interconnecting the first terminals of the N capacitors to the first charge supply terminal and simultaneously electrically interconnecting each of the N capacitors in a parallel circuit between the first and second charge supply terminals of the charging power Source to charge the capacitors to the charging voltage when switched to an electrically closed state, and electrically isolating the capacitors from each other when switched to an electrically open state;

    a plurality of discharging semiconductor switches for interconnecting the second terminal of the capacitor Cn and the first terminal of the capacitor Cn+1 for each of the N capacitors and simultaneously electrically interconnecting each of the N capacitors in a series circuit between the first and second output terminals to produce defibrillation pulses when switched to an electrically closed State, and electrically isolating the capacitors from each other when switched to an electrically open state; and

    a charge dump circuit, including one or more charge dump semiconductor switches in a charge dump current flow path, for simultaneously discharging each of the N capacitors when the charge dump semiconductor switches are switched to an electrically closed state and further including a charge dump semiconductor switch in parallel with each of the N capacitors.

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