Rotary encoder and input device using the same

• US 5,644,127 A
• Filed: 12/22/1994
• Issued: 07/01/1997
• Est. Priority Date: 12/27/1993
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Ohmae, Hideo
• Primary Examiner(s): ALLEN, STEPHONE B
• Application Number:
  US08/361,379
• Time in Patent Office: 922 Days
• Field of Search: 250/231.16, 250/231.18, 345/163, 345/164, 345/167
• US Class Current: 250/231.16
• CPC Class Codes: G01D 5/24476 Signal processing G01D5/2448 - G01D5/24495 take precedence
• CPC Class Codes: G01D 5/2448 Correction of gain, threshold, offset or phase control
• CPC Class Codes: G01D 5/3473 Circular or rotary encoders
• CPC Class Codes: G01D 5/36 Forming the light into pulses
• CPC Class Codes: G06F 3/0312 for tracking the rotation of a spherical or circular member, e.g. optical rotary encoders used in mice or trackballs using a tracking ball or in mouse scroll wheels tracking relative movement in co-operation with a regularly or irregularly patterned surface, e.g. as in optical mice G06F3/0317; constructional details of scroll or thumb-wheels G06F3/0362; optical rotary encoders G01D5/3473
• CPC Class Codes: G06F 3/03543 Mice or pucks G06F3/03541 takes precedence

Abstract

The present invention includes a light receiving unit having a first and second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90°. A first waveform shaping circuit compares the detection signal from the first light receiving element with a reference value and generates a first detection output of a rectangular waveform. A second waveform shaping circuit compares the detection signal from the second light receiving element with the reference value and generates a second detection output of a rectangular waveform. A peak hold circuit receives the detection signal from the first light receiving element and holds the peak value thereof. A reference value generating circuit generates the reference value depending on the peak value held at the peak hold circuit.

Claims

1. A rotary encoder comprising:

a light receiving unit including a first light receiving element and a second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90°

;

a first waveform shaping circuit which compares the detection signal from said first light receiving element with a reference value and generates a first detection output of a rectangular waveform;

a second waveform shaping circuit which compares the detection signal from said second light receiving element with the reference value and generates a second detection output of a rectangular waveform;

a peak hold circuit which receives the detection signal from said first light receiving element and holds the peak value thereof; and

a reference value generating circuit which generates the reference value depending on the peak value held at said peak hold circuit.

2. A rotary encoder according to claim 1, wherein the detection signals are substantially a sinusoidal waveform, and said peak hold circuit includes a comparator which compares the voltage value of the present detection signal outputted from said first light receiving element with the voltage value of the detection signal immediately before the present detection signal, a counter which counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said comparator and a D/A converting circuit which converts the value from said counter to an analog value and outputs the same to said comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said reference value generating circuit as the peak value held in said peak hold circuit.

3. A rotary encoder according to claim 2, further comprising a clock generating circuit which generates said clock pulses and wherein said peak hold circuit further includes a gate circuit which receives said clock pulses and the output from said comparator, passes said clock pulses depending on the output thereof and applies the same to said counter.

4. A rotary encoder according to claim 3 further comprising, a filter circuit for removing noises disposed between said first light receiving element and said peak hold circuit, and wherein said counter is reset at the moment when a power source is switched on.

5. A rotary encoder according to claim 4, wherein said reference value generating circuit generates the reference value by voltage-dividing the held peak value with a voltage dividing rate which is shifted by the corresponding voltage value caused by a dark current flowing through said first light receiving element.

6. A rotary encoder according to claim 1, wherein said peak hold circuit is a first peak hold circuit and further comprising,

a second peak hold circuit which receives the detection signal from said second light receiving element and holds the peak value thereof as a second peak value;

said first peak hold circuit includes a first comparator which compares the voltage value of the present detection signal outputted from said first light receiving element with the voltage value of the detection signal immediately before the present detection signal, a first counter which up-counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said first comparator and a first D/A converting circuit which converts the value from said first counter to an analog value and outputs the same to said first comparator as the voltage value of the detection signal which is sent out to said reference value generating circuit as the first peak value held in said first peak hold circuit, and

said second peak hold circuit includes a second comparator which compares the voltage value of the present detection signal outputted from said second light receiving element with the voltage value of the detection signal immediately before the present detection signal, a second counter which down-counts inputted clock pulses when the voltage level of the present detection signal is lower than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or higher than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said second comparator and a second D/A converting circuit which converts the value from said second counter to an analog value and outputs the same to said second comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said reference value generating circuit as the second peak value held in said second peak hold circuit.

7. A rotary encoder comprising:

a light receiving unit including a first light receiving element and a second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90°

;

a first waveform shaping circuit which compares the detection signal from said first light receiving element with a first reference value and generates a first detection output of a rectangular waveform;

a second waveform shaping circuit which compares the detection signal from said second light receiving element with a second reference value and generates a second detection output of a rectangular waveform;

a first peak hold circuit which receives the detection signal from said first light receiving element and holds the peak value thereof as a first peak value;

a first reference value generating circuit which generates the first reference value depending on the first peak value held at said first peak hold circuit;

a second peak hold circuit which receives the detection signal from said second light receiving element and holds the peak value thereof as a second peak value; and

a second reference value generating circuit which generates the second reference value depending on the second peak value held at said second peak hold circuit.

8. A rotary encoder according to claim 7, wherein said first peak hold circuit includes a first comparator which compares the voltage value of the present detection signal outputted from said first light receiving element with the voltage value of the detection signal immediately before the present detection signal, a first counter which counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said first comparator and a first D/A converting circuit which converts the value from said first counter to an analog value and outputs the same to said first comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said first reference value generating circuit as the first peak value held in said first peak hold circuit, and

said second peak hold circuit includes a second comparator which compares the voltage value of the present detection signal outputted from said second light receiving element with the voltage value of the detection signal immediately before the present detection signal, a second counter which counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said second comparator and a second D/A converting circuit which converts the value from said second counter to an analog value and outputs the same to said second comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said second reference value generating circuit as the second peak value held in said second peak hold circuit.

9. An input device comprising:

first and second rotary encoders each comprising, a light receiving unit including a first and second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90°

;

a first waveform shaping circuit which compares the detection signal from said first light receiving element with a reference value and generates a first detection output of a rectangular waveform;

a second waveform shaping circuit which compares the detection signal from said second light receiving element with the reference value and generates a second detection output of a rectangular waveform;

a peak hold circuit which receives the detection signal from said first light receiving element and holds the peak value thereof; and

a reference value generating circuit which generates the reference value depending on the peak value held at said peak hold circuit;

a first disk rotating mechanism which is disposed for X direction in a XY coordinate system and causes said rotary disk to rotate in said first rotary encoder;

a second disk rotating mechanism which is disposed for Y direction in the XY coordinate system and causes said rotary disk to rotate in said second rotary encoder; and

a ball which is coupled to said first and second disk rotating mechanisms and causes said first and second rotary encoders to rotate.

10. An input device according to claim 9, wherein the detection signals are substantially a sinusoidal waveform, and said peak hold circuit includes a comparator which compares the voltage value of a present detection signal outputted from said first light receiving element with the voltage value of a detection signal immediately before the present detection signal, a counter which counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said comparator and a D/A converting circuit which converts the value from said counter to an analog value and outputs the same to said comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said reference value generating circuit as the peak value held in said peak hold circuit.

11. An input device according to claim 10, further comprising a clock generating circuit which generates said clock pulses and wherein said peak hold circuit further includes a gate circuit which receives said clock pulses and the output from said comparator, passes said clock pulses depending on the output thereof and applies the same to said counter.

12. An input device according to claim 11, further comprising a filter circuit for removing noises disposed between said first light receiving element and said peak hold circuit, and wherein said counter is reset at the moment when a power source is switched on.

13. An input device according to claim 12, wherein said reference value generating circuit generates the reference value by voltage-dividing the held peak value with a voltage dividing rate which is shifted by the corresponding voltage value caused by a dark current flowing through said first light receiving element.

14. An input device according to claim 9, wherein said peak hold circuit is a first peak hold circuit and further comprising,

a second peak hold circuit which receives the detection signal from said second light receiving element and holds the peak value thereof as a second peak value;

said first peak hold circuit includes a first comparator which compares the voltage value of the present detection signal outputted from said first light receiving element with the voltage value of the detection signal immediately before the present detection signal, a first counter which up-counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said first comparator and a first D/A converting circuit which converts the value from said first counter to an analog value and outputs the same to said first comparator as the voltage value of the detection signal which is sent out to said reference value generating circuit as the first peak value held in said first peak hold circuit, and

said second peak hold circuit includes a second comparator which compares the voltage value of the present detection signal outputted from said second light receiving element with the voltage value of the detection signal immediately before the present detection signal, a second counter which down-counts inputted clock pulses when the voltage level of the present detection signal is lower than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or higher than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said second comparator and a second D/A converting circuit which converts the value from said second counter to an analog value and outputs the same to said second comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said reference value generating circuit as the second peak value held in said second peak hold circuit.

15. An input device according to claim 13, wherein said peak hold circuit is a first peak hold circuit and further comprising,

a second peak hold circuit which receives the detection signal from said second light receiving element and holds the peak value thereof as a second peak value;

said first peak hold circuit includes a first comparator which compares the voltage value of the present detection signal outputted from said first light receiving element with the voltage value of the detection signal immediately before the present detection signal, a first counter which up-counts inputted clock pulses when the voltage level of the present detection signal is higher than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or lower than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said first comparator and a first D/A converting circuit which converts the value from said first counter to an analog value and outputs the same to said first comparator as the voltage value of the detection signal which is sent out to said reference value generating circuit as the first peak value held in said first peak hold circuit, and

said second peak hold circuit includes a second comparator which compares the voltage value of the present detection signal outputted from said second light receiving element with the voltage value of the detection signal immediately before the present detection signal, a second counter which down-counts inputted clock pulses when the voltage level of the present detection signal is lower than the voltage level of the detection signal immediately before the present detection signal and terminates the counting when the voltage level of the present detection signal becomes equal to or higher than the voltage level of the detection signal immediately before the present detection signal depending on the comparison result of said second comparator and a second D/A converting circuit which converts the value from said second counter to an analog value and outputs the same to said second comparator as the voltage value of the detection signal immediately before the present detection signal which is sent out to said reference value generating circuit as the second peak value held in said second peak hold circuit.