Dynamic threshold voltage scheme for low voltage CMOS inverter
First Claim
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1. A low voltage inverter, comprising:
- a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and
a back-gate biasing circuit consisting of a capacitor and a load, wherein said capacitor is connected between an input terminal of said CMOS inverter and one of bulks of said transistors for biasing via said load.
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Abstract
The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.
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Citations
10 Claims
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1. A low voltage inverter, comprising:
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a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a capacitor and a load, wherein said capacitor is connected between an input terminal of said CMOS inverter and one of bulks of said transistors for biasing via said load. - View Dependent Claims (2, 3, 4, 5)
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6. A low voltage inverter, comprising:
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a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a first capacitor, a second capacitor, a first load and a second load;
wherein said first capacitor is connected between an input terminal of said CMOS inverter and a bulk of said PMOS transistor, said second capacitor is connected between said input terminal and a bulk of said NMOS transistor, said first load biases said bulk of said PMOS transistor, and said second load biases said bulk of said NMOS transistor. - View Dependent Claims (7, 8, 9, 10)
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Specification